NDLI: Extracting RTL models from transistor netlists

Content Provider	IEEE Xplore Digital Library
Author	Singh, K.J. Subrahmanyam, P.A.
Copyright Year	1997
Description	Author affiliation: AT&T Bell Labs., Holmdel, NJ, USA (Singh, K.J.; Subrahmanyam, P.A.)
Abstract	This paper addresses the problem of deriving a register-transfer level (RTL) model from a transistor-level circuit. Using existing techniques, the transistor-level circuit is converted into a relation that describes the evolution of the signals in the circuit with respect to the simulator clock. This simulation relation is then manipulated to derive the stable behavior of the circuit. Given this stable behavior and information about the clocking scheme, we determine if the circuit is combinational, asynchronous or synchronous. For combinational and synchronous circuits we derive an equivalent register-transfer level model. This development enables full-custom circuit designers to use tools that were till now available only to designers working at the gate-level. The algorithm has been successfully used to characterize several custom designs, as well as the entire AT&T standard-cell library.
Starting Page	11
Ending Page	17
File Size	776799
Page Count	7
File Format	PDF
ISBN	0818682000
ISSN	10636757
DOI	10.1109/ICCAD.1995.479879
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-11-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit simulation Computational modeling Algorithm design and analysis Clocks Logic circuits Pattern matching Design optimization Switches Voltage Software libraries
Content Type	Text
Resource Type	Article

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