NDLI: An iterative gate sizing approach with accurate delay evaluation

Content Provider	IEEE Xplore Digital Library
Author	Guangqiu Chen Onodera, H. Tamaru, K.
Copyright Year	1997
Description	Author affiliation: Dept. of Electron. & Commun., Kyoto Univ., Japan (Guangqiu Chen; Onodera, H.; Tamaru, K.)
Abstract	This paper introduces a new gate sizing approach with accurate delay evaluation. The approach solves gate sizing problems by iterating local sizing results from linear programming within mall variable ranges of gate sizes. In each iterative step, variable ranges of gate sizes are updated according to the result from a previous step. Solutions with accurate delay evaluation which consider input signal slopes and separately evaluate rising and falling delays are obtained after several iterative steps. A speedup technique is used to pick out gates actually involved in each local sizing step so as to reduce CPU time. Experiments on sample circuits show that our approach can provide solutions with smaller circuit area than conventional approaches for the same circuit delay or provide solutions under tight delay constraints where conventional approaches can nor reach. Moreover, our approach is faster than the conventional approaches for most circuits, especially under loose delay constraints.
Starting Page	422
Ending Page	427
File Size	602090
Page Count	6
File Format	PDF
ISBN	0818682000
ISSN	10636757
DOI	10.1109/ICCAD.1995.480150
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-11-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Iterative methods Timing Linear programming Piecewise linear approximation Piecewise linear techniques Delay effects Linear approximation Circuit testing Central Processing Unit Constraint optimization
Content Type	Text
Resource Type	Article

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