NDLI: Bonding copper low-k die with bond pads over active circuitry (pads on I/O)

Content Provider	IEEE Xplore Digital Library
Author	Low, Q.H. Othieno, M. McCormick, J.
Copyright Year	2004
Description	Author affiliation: LSI Logic Corp., Milpitas, CA, USA (Low, Q.H.; Othieno, M.; McCormick, J.)
Abstract	Summary form only given. As the demand for smaller die with high input/output (I/O) connections continues to rise, new innovations on die bond pad placement and design are required. Some of LSI Logic's customers are currently requesting die with as many as 1200 bonding pads on an 8 mm die. To meet customer requirements as well as enhancing die technology, LSI Logic has developed an innovative way of increasing die bond pad density without increasing the die size by putting bond pads over active circuitry on low-k copper die. Moreover, this new innovation can also be used to increase I/O count while reducing the die size. LSI Logic refers to this new technology as pads on I/O. The challenges presented in bonding low-k die are well documented. These challenges include, but are not limited to, pad metal cracking, pad metal lifting on the copper/low-k, delamination in low-k layers, and changes in the I/O electrical parametric performance. Before die fabrication, the electrical impact of locating the pads over I/O was evaluated. Additionally, finite element analysis was also performed on the new pad structures to determine the impact of mechanical forces due to the bonding forces and thermal loads due to the epoxy materials (die attach/mold compound) used. The parameters obtained from these evaluations were used to develop a suitable test design vehicle that is capable of evaluating most of the major failures that are involved in assembly and test of low-k die with pads on I/O. Test chips with range of 3 to 8 metal layers were fabricated using black diamond low-k. The dies were assembled on a 14/spl times/20 mm 64 PQFP and 35mm 492 PBGA using special low stress molding compound and die attach epoxy. In order to obtain a suitable bonding parameter window, a 9-leg design of experiment (DOE) was performed using the ball shear test (BST), the ball pull test (BPT), and the pad-cratering test (PCT) as the input parameters. Additionally, bond pad cross sections were evaluated to determine the presence of cracks in the underlying copper metallization and low-k dielectric layers. From the DOE analysis, optimized bonding parameters (power, force, time, & temperature) were determined. The optimized parameters were used in the assembly of qualification units. The assembled units were subjected to a JEDEC level 3 qualification in which temperature cycling condition B (TCB), biased temperature humidity (BTH), and high temperature operation life (HTOL) tests were performed to induce failures. Electrical tests and acoustic microscopy (SONOSCAN) was performed on the units to determine the presence of opens/shorts/delamination in the units. HSPICE was also used to compare the parametric shifts between standard low-k die with peripheral pads and the new design with wire pads on I/O. From the test data, it is observed that the wirebond production monitors (BST, BPT, and PCT) were easily satisfied. Package cross-section pictures taken by an SEM does not indicate damage in the underlying layers. In addition, it is found from HSPICE evaluation that there are no shifts in the monitored I/O leakage electrical data. Currently, LSI Logic is in full production with copper low-k pads on I/O die. These die are fabricated with 3-rows of staggered bonding pads which are all located on the active circuitry. This has resulted in approximately 40 percent reduction in die size for high pin-count wire bonded packages.
Sponsorship	IEEE CPMT SEMI
File Size	226082
File Format	PDF
ISBN	0780385829
ISSN	10898190
DOI	10.1109/IEMT.2004.1321621
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-07-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bonding Copper Circuits Large scale integration Assembly Temperature Logic Performance evaluation Acoustic testing Technological innovation
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electrical and Electronic Engineering

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