NDLI: Pre-project facility and layout planning for setting up cost effective wafer bumping processes

Content Provider	IEEE Xplore Digital Library
Author	Wu, M. Jin, Y.G. Quek, S.T. Huang, S.
Copyright Year	2003
Description	Author affiliation: ST Assembly Test Service Ltd., Singapore, Singapore (Wu, M.; Jin, Y.G.; Quek, S.T.; Huang, S.)
Abstract	With the emergence of flip chip technologies in semiconductor assembly, a great deal of attention has been given to infrastructures such as wafer bumping services, equipment manufacturers, material and substrate suppliers. Little has been said about facility planning and design for flip chip processes. When rapid shifts in technology take place, optimum planning of facility layout is of great importance for productive manufacturing processes in term of cycle time, yield, quality control, and sustainability. This paper explores a facility layout design using Simplified Systematic Layout Planning (SSLP) techniques prior to the wafer bumping setup. Other techniques such as experiential, cloning, strategic or Bottom-up are difficult, if not impossible, to be applied in a process with new technological requirements. In this study, a "ball room" design is compared with "cellular" design by analyzing four basic elements: space planning units (SPUs), affinities, space, and constraints at the Macro-Space Plan level. The cellular layout arrangement is more cost effective than the ballroom design, however at the expense of its flexibility for future changes and upgrading. In this case, a low value-added space ratio is used to compensate the inflexibility. Differentiated cleanroom modules are designed for the sub-processes of wafer bumping so that the areas of high-grade cleanroom (ISO Class 5) are minimized. The final layout plan is further evaluated by using positive-negative-interesting (PNI) and material flow analysis (MFA) tools. In addition, special attention is paid to the integration of new and existing processes.
Starting Page	351
Ending Page	356
File Size	463386
Page Count	6
File Format	PDF
ISBN	0780379330
ISSN	10898190
DOI	10.1109/IEMT.2003.1225928
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-07-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Process planning Costs Space technology Flip chip Assembly Semiconductor device manufacture Semiconductor materials Substrates Technology planning Manufacturing processes
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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