NDLI: Study of non-solder, low cost and high performance flip chip QFN package using ultra thin Pd PPF

Content Provider	IEEE Xplore Digital Library
Author	Se Chuel Park Chullae Cho Sung-Kwan Paek
Copyright Year	2003
Description	Author affiliation: Semicond. Mater. Div., Samsung Techwin Co., Ltd., Gyeongsangnam-Do, South Korea (Se Chuel Park; Chullae Cho; Sung-Kwan Paek)
Abstract	For the development of semiconductor package, size reduction and high performance are driving forces. As increasing hand held products and green round issue, all package companies are interesting in study of package using lead free solder. As the today's package trend, many kinds of flip chip packages are developed using lead free solder. In most of flip chip packages, lead free solder or Au has been employed mainly as wafer bump, and Sn or Ag plated leadframe based on copper as a substrate. Solder as an interconnection material has been adopted. This study describes the performance of low cost, non-solder and green round package using flip chip interconnection technology on a Pd pre-plated leadframe (Pd PPF). The conventional leadframe couldn't be heated over 270 because of copper peel off. Although Pd-PPF could be workable in higher temperature than other type Cu leadframes, Conventional Pd-PPF showed that the poor thermal resistance for flip chip bonding process at high temperature. Therefore, in this study, newly developed a high quality and ultra thin Pd-PPF (AuAg finished Pd PPF) could provide proper surface condition and soluble substances. This leadframe could be applied to flip chip interconnection in wide temperature range. In conception of low cost, the electroless Ni/Au bump was used for flip chip interconnection with AuAg finished Pd PPF. The shear force of direct-bonded package was 23.05 mgf//spl mu/m/sup 2/. We used thermal compression bonding method and bonding condition is as following: chip temperature 380 and leadframe 380. As leadframe temperature being increased, shear force of the package was very steeply increased. The interconnected layer between the bump and the pre-plated leadframe was composed of Ni/AuAg/Pd/Ni.
Starting Page	31
Ending Page	37
File Size	643405
Page Count	7
File Format	PDF
ISBN	0780379330
ISSN	10898190
DOI	10.1109/IEMT.2003.1225874
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-07-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Flip chip Lead Semiconductor device packaging Temperature Environmentally friendly manufacturing techniques Copper Gold Thermal resistance Bonding
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electrical and Electronic Engineering

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