NDLI: Chip scale packaging reliability

Content Provider	IEEE Xplore Digital Library
Author	Quinones, H. Babiarz, A.
Copyright Year	2000
Description	Author affiliation: Asymtek Headquarters, Carlsbad, CA, USA (Quinones, H.)
Abstract	The introduction of underfill in flip chip packaging gave solder interconnect technology an unforeseen mechanical robustness and increased flip chip solder fatigue resistance. Derivatives from this technology (e.g. PBGA, CBGA, CSP, etc.) have been developed in recent years. New interconnect geometry is used extensively with moderate success in overcoming large mismatches in component displacements during temperature excursions and supports larger loading (e.g. heatsinks, etc.). However, environments and testing qualifications for these packages are becoming increasingly demanding. Failure mechanisms thought to have been eliminated, or at least alleviated to a manageable extent by new package designs, are again threatening integrity and reliability. Chip scale packages, first designed to eliminate the need for encapsulation, to be SMT process compatible, and to have good handling properties, etc., face serious reliability problems. High-power devices that require massive heatsinks could lead to cyclic creep phenomena due to the static load applied by these heat spreaders. Dynamic loading induced by mechanical vibration and impact shock results in reliability detractors for CSP and DCA packages. Analytical models and simulation of these mechanisms are proposed. This paper addresses failure mechanisms of CSP and DCA packages, and the effects and advantages of underfilling. We present and propose the encapsulation process as a natural and proven method to ensure reliable packages that overcome reliability threats. Models supporting encapsulation as a solution are presented. Data comparing encapsulated and nonencapsulated packages is also given.
Starting Page	398
Ending Page	405
File Size	653562
Page Count	8
File Format	PDF
ISBN	0780366549
DOI	10.1109/EMAP.2000.904188
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-11-30
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Chip scale packaging Encapsulation Flip chip Heat sinks Failure analysis Analytical models Robustness Fatigue Geometry Temperature
Content Type	Text
Resource Type	Article

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