NDLI: Flip-chip soldering to bare copper circuits

Content Provider	IEEE Xplore Digital Library
Author	Ingraham, A.P. McCreary, J.M. Varcoe, J.A.
Copyright Year	1990
Description	Author affiliation: IBM Corp. Endicott, NY, USA (Ingraham, A.P.; McCreary, J.M.; Varcoe, J.A.)
Abstract	The authors describe a process for providing high-yield/high-reliability C4 (controlled collapse chip connection) joining to bare copper circuitry. A study was undertaken in the course of implementing a major change in IBM's metallized ceramic (MC) and metallized ceramic-polyimide (MCP) production line. It involved joining chips with 95/5 Pb/Sn C4 solder bumps to bare copper pads on substrates to replace dip-tinned substrates with 90/10 pB/Sn-coated pads. An extensive analysis of the C4 interconnection was carried out. Over 30000 chips were joined to ceramic substrates to characterize wetting to the copper pads, evaluate C4 fatigue life, and assess any effect on reliability of natural and artificially induced defects in the C4 columns or wetted pad surface. C4 defect levels and C4 fatigue testing were equivalent for both types of product, tinned and untinned pads. Solder wetting to a clean copper surface was shown to be as good as wetting to a solder-coated surface. The reliability effect on the product due to partial wets was found to be insignificant. The technique for C4 interconnection joining to copper pads has been successfully implemented in many manufacturing sites.<>
Starting Page	333
Ending Page	337
File Size	1365090
Page Count	5
File Format	PDF
DOI	10.1109/ECTC.1990.122211
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-05-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Soldering Copper Surface cleaning Metallization Ceramics Integrated circuit interconnections Fatigue Production Tin Testing
Content Type	Text
Resource Type	Article

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