NDLI: Parametric shifts in devices: role of packaging variables and some novel solutions

Content Provider	IEEE Xplore Digital Library
Author	Pendse, R. Jennings, D.
Copyright Year	1990
Description	Author affiliation: Nat. Semicond. Corp., Santa Clara, CA, USA (Pendse, R.; Jennings, D.)
Abstract	The resistance-shift phenomena typically encountered in precision analog devices such as operational amplifiers which use the BiFET structure is discussed and resolved. A test chip consisting of fourteen implant resistors acting as piezoelectric strain gauges and temperature-sensing diodes for accurate recording of chip temperature was designed and fabricated. The incremental stressing effect of each packaging operation performed in sequence was measured and characterized using the chip. It was found that the chip-attachment operation results in small residual tensile stress at the chip surface corresponding to positive resistance shifts in the P-type regions of the chip. This stress state prevails in most ceramic packages; however; in plastic packages, severe compressive tractions resulting from the shrinkage of the plastic change the resistance shifts to large negative values for P-type resistors. This clearly limits the merits of low-stress die attach in plastic packages. The merits of some commonly used stress-reduction schemes such as compliant die attach, low-stress encapsulents, and die coatings were assessed. Some novel solutions to package stress, such as thermoplastic die attachment, five-sided coating, and silicon pad, are demonstrated.<>
Starting Page	322
Ending Page	326
File Size	485637
Page Count	5
File Format	PDF
DOI	10.1109/ECTC.1990.122209
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-05-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Plastic packaging Resistors Tensile stress Surface resistance Microassembly Coatings Operational amplifiers Testing Implants Capacitive sensors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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