NDLI: Characteristics of CMOS device isolation for the ULSI age

Content Provider	IEEE Xplore Digital Library
Author	Bryant, A. Hansch, W. Mii, T.
Copyright Year	1994
Description	Author affiliation: Microelectron Div., IBM Corp., USA (Bryant, A.)
Abstract	Scaling requirements for abrupt active-isolation transitions, isolation depth, and isolation planarity are discussed quantitatively. We review how LOCOS and STI isolation are being improved to meet these requirements. Independent of fabrication techniques, we see that a necessary consequence of achieving the desired narrow isolation and abrupt transitions is a discrete edge parasitic. We show that the edge parasitic can be distinguished from the planar channel and can be characterized separately. Edge device sensitivities are investigated with experiment and simulation to show that design and process control of the discrete edge parasitic will be a significant thrust of device engineering for future isolation technologies.<>
Starting Page	671
Ending Page	674
File Size	405881
Page Count	4
File Format	PDF
ISBN	0780321111
ISSN	01631918
DOI	10.1109/IEDM.1994.383292
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-12-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Ultra large scale integration Random access memory MOSFET circuits Isolation technology CMOS technology Silicon Surface topography Etching Geometry Implants
Content Type	Text
Resource Type	Article
Subject	Materials Chemistry Electronic, Optical and Magnetic Materials Condensed Matter Physics Electrical and Electronic Engineering

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