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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Murugesan, M. Bea, J.C. Kino, H. Ohara, Y. Kojima, T. Noriki, A. Lee, K.W. Kiyoyama, K. Fukushima, T. Nohira, H. Hattori, T. Ikenaga, E. Tanaka, T. Koyanagi, M. |
| Copyright Year | 2009 |
| Description | Author affiliation: JASRI, Sayo-gun, Hyogo 679-5198 Japan (Ikenaga, E.) || Dept. of Bioengineering & Robotics, Tohoku Univ., 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai, 980-8579, Japan (Murugesan, M.; Bea, J.C.; Kino, H.; Ohara, Y.; Kojima, T.; Noriki, A.; Lee, K.W.; Kiyoyama, K.; Fukushima, T.; Tanaka, T.; Koyanagi, M.) || New Industry Creation Hatchery Center, Tohoku Univ., Japan (Hattori, T.) || Tokyo City, Univ., 1-28-1 Tamazutsumi, 158-8557, Japan (Nohira, H.) |
| Abstract | Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated. The remnant stress left after wafer thinning was evaluated by micro-Raman spectroscopy (µRS) and XPS. It was found that the mechanical stress remained in the back surface of Si substrate after wafer thinning and a part of this mechanical stress appeared in the surface of Si substrate. The metal contamination in such thinned Si substrate has been evaluated by a C-t method. It was found that the carrier generation lifetime was degraded by Cu diffused into Si substrate at relatively low temperature of 200 °C. The mechanical stress/strain in the thinned Si substrate after wafer bonding was also evaluated to investigate the influences of metal microbumps to the thinned Si substrate. It was found that the local mechanical stress was generated in the Si substrate surface by the microbumps. This local stress caused a 3% change in the ON current of MOS transistor. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 1801064 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424456390 |
| e-ISBN | 9781424456413 |
| e-ISBN | 9781424456406 |
| DOI | 10.1109/IEDM.2009.5424348 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-12-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Stress Capacitive sensors Wafer bonding Through-silicon vias Surface contamination Large scale integration Fabrication Spectroscopy Degradation Temperature |
| Content Type | Text |
| Resource Type | Article |
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