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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Arnaud, F. Thean, A. Eller, M. Lipinski, M. Teh, Y.W. Ostermayr, M. Kang, K. Kim, N.S. Ohuchi, K. Han, J.-P. Nair, D.R. Lian, J. Uchimura, S. Kohler, S. Miyaki, S. Ferreira, P. Park, J.-H. Hamaguchi, M. Miyashita, K. Augur, R. Zhang, Q. Strahrenberg, K. ElGhouli, S. Bonnouvrier, J. Matsuoka, F. Lindsay, R. Sudijono, J. Johnson, F.S. Ku, J.H. Sekine, M. Steegen, A. Sampson, R. |
| Copyright Year | 2009 |
| Description | Author affiliation: Chartered Semiconductor Manufacturing, IBM Semiconductor Research and Development Center (SRDC), 2070 route 52, Hopewell Junction, NY 12533, USA (Teh, Y.W.; Kim, N.S.; Sudijono, J.) || GlobalFoundries, IBM Semiconductor Research and Development Center (SRDC), 2070 route 52, Hopewell Junction, NY 12533, USA (Augur, R.; Johnson, F.S.) || Samsung Electronics, IBM Semiconductor Research and Development Center (SRDC), 2070 route 52, Hopewell Junction, NY 12533, USA (Kang, K.; Park, J.-H.; Ku, J.H.) || Toshiba Corporation, IBM Semiconductor Research and Development Center (SRDC), 2070 route 52, Hopewell Junction, NY 12533, USA (Ohuchi, K.; Uchimura, S.; Hamaguchi, M.; Miyashita, K.; Matsuoka, F.) || STMicroelectronics, IBM Semiconductor Research and Development Center (SRDC), 2070 route 52, Hopewell Junction, NY 12533, USA (Arnaud, F.; Kohler, S.; Ferreira, P.; ElGhouli, S.; Bonnouvrier, J.; Sampson, R.) || NEC-EL, IBM Semiconductor Research and Development Center (SRDC), 2070 route 52, Hopewell Junction, NY 12533, USA (Miyaki, S.; Sekine, M.) || Infineon Technologies, IBM Semiconductor Research and Development Center (SRDC), 2070 route 52, Hopewell Junction, NY 12533, USA (Eller, M.; Lipinski, M.; Ostermayr, M.; Han, J.-P.; Lian, J.; Strahrenberg, K.; Lindsay, R.) || IBM Microelectronics, IBM Semiconductor Research and Development Center (SRDC), 2070 route 52, Hopewell Junction, NY 12533, USA (Thean, A.; Nair, D.R.; Zhang, Q.; Steegen, A.) |
| Abstract | In this paper, we present a cost-effective 28nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 $kGate/mm^{2},$ and, using the ARM Cortex-R4F as a reference, we report achievement of an overall 2.4x area reduction in 28nm from 45nm technology. Our high-density SRAM bit-cell (area= $0.120mm^{2})$ has a demonstrated Static Noise Margin (SNM) of 213mV at 1V. Fully compatible with power/leakage management techniques intensively used in low power designs, the transistor drive currents are increased +35% & +10%, for nFET and pFET respectively, with respect to a 28nm LP poly/SiON reference [3]. Compatible with LP system-on-chip requirements, ultra low-cost, high performance analog devices are reported which leverage a dramatic improvement in matching factor (AVT∼2mV.um) versus our previously-reported result [2]. An optimized interconnection scheme based on Extreme Low k (ELK) dielectric (k∼2.4) and advanced metallization allows high density wiring with competitive R-C versus our previous technology. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 1109154 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424456390 |
| e-ISBN | 9781424456413 |
| e-ISBN | 9781424456406 |
| DOI | 10.1109/IEDM.2009.5424255 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-12-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | CMOS technology Costs High K dielectric materials High-K gate dielectrics Random access memory Energy management Power system management System-on-a-chip Metallization Wiring |
| Content Type | Text |
| Resource Type | Article |
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