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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Charbuillet, C. Monfray, S. Dubois, E. Bouillon, P. Judong, F. Skotnicki, T. |
| Copyright Year | 2006 |
| Description | Author affiliation: STMicroelectronics, Crolles (Charbuillet, C.; Monfray, S.) |
| Abstract | This papers presents new results on silicon I-MOS devices, (where the source and the drain are doped of opposite type) obtained by an adaptation of a conventional CMOS process. Fabricated devices are fully functional down to 55nm of gate length, but the influence of the gate becomes strongly reduced for shorter devices due to technological limitations. Nevertheless, the smallest device, with a 17nm gate length and with an avalanche threshold of 5.3V, is reported. The corresponding output current-voltage features an equivalent resistance as low as 66 Omegamiddotmum. For all devices, the maximum current is only limited by the contacts destruction, positioning the measured value of 4700 muA/mum among the highest ever reported for a MOS device. In addition, it is shown that the extrapolated $I_{on}/I_{off$ figure of merit is close to complying with the specifications imposed to the HP flavor of the ITRS'05 roadmap |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 384672 |
| Page Count | 4 |
| File Format | |
| ISBN | 142440438X |
| DOI | 10.1109/IEDM.2006.346983 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-12-11 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Impact ionization Resists Silicon CMOS process CMOS technology Current measurement Electrical resistance measurement Position measurement MOS devices Power dissipation |
| Content Type | Text |
| Resource Type | Article |
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