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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Charbuillet, C. Dubois, E. Monfray, L. Bouillon, P. Skotnicki, T. |
| Copyright Year | 2006 |
| Description | Author affiliation: STMicroelectron., Crolles (Charbuillet, C.) |
| Abstract | This paper reports on a new process to realize impact-ionization MOSFETs (I-MOS) with gate length down to 50nm. This process is an adaptation of a standard 90nm flow, which assures a perfect compatibility with conventional CMOS. The definition of the $n^{+}$ and $p^{+}$ regions of the I-MOS is based on two shifted lithography steps using the standard source/drain mask. An analytical model for the breakdown voltage of an ID p-i-n diode has also been developed to express the breakdown voltage of I-MOS devices as a function of the gate and intrinsic lengths, and the doping level. This model has been validated by the experimental results. An extremely low experimental device resistance (270 Omega.mum) is reported at a gate length of 55 nm, placing the I-MOS architecture favorably with respect to ITRS requirements. This performance is explained by the much higher carrier concentration generated by impact ionization when compared to the conventional MOS. Channel resistance is found negligible and current only limited by the source/drain (S/D) resistance |
| Starting Page | 299 |
| Ending Page | 302 |
| File Size | 4466222 |
| Page Count | 4 |
| File Format | |
| ISBN | 1424403014 |
| ISSN | 19308876 |
| DOI | 10.1109/ESSDER.2006.307697 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-09-19 |
| Publisher Place | Switzerland |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Fabrication MOSFETs CMOS process Lithography P-i-n diodes Impact ionization Leakage current Silicon Voltage Conducting materials |
| Content Type | Text |
| Resource Type | Article |
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