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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chang Woo Oh Na Young Kim Sung Hwan Kim Yong Lack Choi Sung In Hong Hyun Jun Bae Jin Bum Kim Kong Soo Lee Yong Seok Lee Nam Myun Cho Dong-Won Kim Donggun Park Byung-Il Ryu |
| Copyright Year | 2006 |
| Description | Author affiliation: Device Res. Team, Samsung Electron. Co., Yongin (Chang Woo Oh; Na Young Kim; Sung Hwan Kim; Yong Lack Choi; Sung In Hong; Hyun Jun Bae) |
| Abstract | In this article, we report improved results of 4-bit double SONOS memories (DSMs) with 4-storage nodes through the optimization of ONO layer thicknesses for front and back sides. They show more balanced characteristics between the front and back channels, higher VTH shifts above 2.4V, larger read margins above 1.6V, better endurance, and longer retention time than our previous results. In addition, we also propose and demonstrate a highly scaled 4-bit DSM using multi-level technology. The $V_{TH}$ shifts above 4V splitting into 4 levels without noticeable interferences are achieved. Each nodes show clear 4 levels with good retention |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 654244 |
| Page Count | 4 |
| File Format | |
| ISBN | 142440438X |
| DOI | 10.1109/IEDM.2006.346947 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-12-11 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | SONOS devices Interference Research and development Flash memory Nonvolatile memory Scalability MOSFET circuits |
| Content Type | Text |
| Resource Type | Article |
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