NDLI: High gain, wide margin Josephson junction OR and AND gates

Content Provider	IEEE Xplore Digital Library
Author	Tsing-Chow Wang Josephs, R.M. Stein, B.F. Young, P.L. Flanery, W.E.
Copyright Year	1981
Description	Author affiliation: Sperry Univac, Blue Bell, PA (Tsing-Chow Wang)
Abstract	A new group of high gain and wide margin Josephson Junction direct coupled isolation devices using a novel amplification scheme is described. The group includes a three Josephson Junction OR (3J/OR) gate and a four Josephson Junction AND (4J/AND) gate. DC threshold curves of both devices have been calculated. The optimized threshold for the 3J/OR shows a 30 percent improvement in margin with respect to that of Direct Coupled Logic (DCL). For the 4J/AND, the gain is improved by a factor of 2 over that of the non-linear current injection interferometer devices and the discrimination between one and two inputs is preserved. Simulations of both the 3J/OR and 4J/AND exhibit approximately square current transfer curves with good input and output isolation. For a fan-in of two and a fan-out of three, the 3J/OR gate gives an average switching delay of 31ps and a power dissipation of 3.6µw, and the 4J/AND gate gives a switching delay of 41ps and a power dissipation of 3.8µw.
Starting Page	118
Ending Page	121
File Size	289047
Page Count	4
File Format	PDF
DOI	10.1109/IEDM.1981.190015
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1981-12-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Josephson junctions Logic devices Switches Electronics packaging Delay Power dissipation Voltage control Zero voltage switching Coupling circuits Magnetic switching
Content Type	Text
Resource Type	Article

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