NDLI: A highly manufacturable low power and high speed HfSiO CMOS FET with dual poly-Si gate electrodes

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Ambient intelligence - key technologies in the information age

Requirements and strategies for semiconductor technologies for mobile communication terminals

Nano transformations: a future of our making

Fully working 1.25 /spl mu/m/sup 2/ 6T-SRAM cell with 45 nm gate length triple gate transistors

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Device properties in 90 nm and beyond and implications on circuit design

Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs

Fully-depleted strained-Si on insulator NMOSFETs without relaxed SiGe buffers

Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs

Substrate-strained silicon technology: process integration [CMOS technology]

Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology

Comprehensive low-frequency and RF noise characteristics in strained-Si NMOSFETs

Process-strained Si (PSS) CMOS technology featuring 3D strain engineering

High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

ALD HfO/sub 2/ using heavy water (D/sub 2/O) for improved MOSFET stability

The impact of sub monolayers of HfO/sub 2/ on the device performance of high-k based transistors [MOSFETs]

Problems with metal-oxide high-/spl kappa/ dielectrics due to 1/t dielectric relaxation current in amorphous materials

High-k dielectrics and MOSFET characteristics

Thermally robust high quality HfN/HfO/sub 2/ gate stack for advanced CMOS devices

Nitrogen profile control by plasma nitridation technique for poly-Si gate HfSiON CMOSFET with excellent interface property and ultra-low leakage current

Effect of Hf-N bond on properties of thermally stable amorphous HfSiON and applicability of this material to sub-50nm technology node LSIs

SiGe HBT and BiCMOS technologies

A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs

SiGe:C BiCMOS technology with 3.6 ps gate delay

Ultra low power SiGe:C HBT for 0.18 /spl mu/m RF-BiCMOS

Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm gate CMOS

New method for temperature-dependent thermal resistance and capacitance accurate extraction in high-voltage DMOS transistors

Novel self-assembled ultra-low-k porous silica films with high mechanical strength for 45 nm BEOL technology

A new plasma-enhanced co-polymerization (PCP) technology for reinforcing mechanical properties of organic silica low-k/Cu interconnects on 300 mm wafers

Bottom-up fill of copper in high aspect ratio via holes by electroless plating

Low-pressure CMP for 300-mm ultra low-k (k=1.6-1.8)/Cu integration

Experimental and Monte Carlo analysis of drain-avalanche hot-hole injection for reliability optimization in Flash memories

A new statistical model to extract the stress induced oxide trap number and the probability density distribution of the gate current produced by a single trap

Statistical simulations to inspect and predict data retention and program disturbs in flash memories

Reliability models of data retention and read-disturb in 2-bit nitride storage flash memory cells

Novel operation schemes to improve device reliability in a localized trapping storage SONOS-type flash memory

Reliability study of CMOS FinFETs

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An investigation of the damage mechanisms in impact ionization-induced "mixed-mode" reliability stressing of scaled SiGe HBTs

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NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs]

Effect of pMOST bias-temperature instability on circuit reliability performance

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High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering

A highly manufacturable low power and high speed HfSiO CMOS FET with dual poly-Si gate electrodes

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New approaches to improve the endurance of TiN/HfO/sub 2//TiN capacitor during the back-end process for 70nm DRAM device

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3-D Monte Carlo simulations of FinFETs

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Investigation of performance limits of germanium double-gated MOSFETs

A computational study of ballistic silicon nanowire transistors

Scaling analysis of phase-change memory technology

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Electrical degradation mechanisms of RF power GaAs PHEMTs

Performance enhancement of 0.13/spl mu/m In/sub 0.65/GaAs PHEMT by reduction of parasitic effect using novel double-deck shaped (DDS) gate structure

Improvement of circuit-speed of HEMTs IC by reducing the parasitic capacitance

High frequency InAs-channel HEMTs for low power ICs

Vertical multi-RESURF MOSFETs exhibiting record low specific resistance

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Single crystal SiC capacitive pressure sensor at 400/spl deg/C

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Inversion channel mobility in high-/spl kappa/ high performance MOSFETs

Unified mobility model for high-/spl kappa/ gate stacks [MISFETs]

Low noise balanced-CMOS on Si(110) surface for analog/digital mixed signal circuits

Experimental study on carrier transport mechanisms in double- and single-gate ultrathin-body MOSFETs - Coulomb scattering, volume inversion, and /spl delta/T/sub SOI/-induced scattering

Physical mechanism for high hole mobility in [110]-surface strained- and unstrained-MOSFETs

Impact ionization in strained-Si/SiGe heterostructures

70nm NAND flash technology with 0.025 /spl mu/m/sup 2/ cell size for 4Gb flash memory

90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F/sup 2//bit and programming throughput of 10 MB/s

An 8F/sup 2/ MRAM technology using modified metal lines

MRAM with lamellar structure as free layer

Noble FeRAM technologies with MTP cell structure and BLT ferroelectric capacitors

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Robust porous MSQ (k=2.3, e=12 GPa) for low-temperature (<350/spl deg/C) Cu/low-k integration using ArF resist mask process

Reemergence of the surface-potential-based compact MOSFET models

New compact model for induced gate current noise [MOSFET]

Hydrodynamic modeling of RF noise in CMOS devices

Predictive spiral inductor compact model for frequency and time domain

Voltage and temperature dependence of capacitance of high-k HfO/sub 2/ MIM capacitors: a unified understanding and prediction

Thermal analysis of ultra-thin body device scaling [SOI and FinFet devices]

A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management

Writing current reduction for high-density phase-change RAM

A GeSbTe phase-change memory cell featuring a tungsten heater electrode for low-power, highly stable, and short-read-cycle operations

Novel cell structure of PRAM with thin metal layer inserted GeSbTe

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Scaled 2bit/cell SONOS type nonvolatile memory technology for sub-90nm embedded application using SiN sidewall trapping structure

A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory

Critical assessment of soft breakdown stability time and the implementation of new post-breakdown methodology for ultra-thin gate oxides [MOSFET]

Reliability issues for high-k gate dielectrics

Analysis of charge trapping and breakdown mechanism in high-k dielectrics with metal gate electrode using carrier separation

Degradation mechanism of HfSiON gate insulator and effect of nitrogen composition on the statistical distribution of the breakdown

Effect of bulk trap density on HfO/sub 2/ reliability and yield

Characterization and comparison of the charge trapping in HfSiON and HfO/sub 2/ gate dielectrics

Improvement of NBTI and electrical characteristics by ozone pre-treatment and PBTI issues in HfAlO(N) high-k gate dielectrics

Integrated sensor and electronics processing for >10^8 "iMEMS" inertial measurement unit components

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A highly manufacturable low power and high speed HfSiO CMOS FET with dual poly-Si gate electrodes

Content Provider	IEEE Xplore Digital Library
Author	Iwamoto, T. Ogura, T. Terai, M. Watanabe, H. Watanabe, H. Ikarashi, N. Miyamura, M. Tatsumi, T. Saitoh, M. Morioka, A. Watanabe, K. Saito, Y. Yabe, Y. Ikarashi, T. Masuzaki, K. Mochizuki, Y. Mogami, T.
Copyright Year	2003
Description	Author affiliation: Silicon Syst. Res. Labs., NEC Corp., Kanagawa, Japan (Iwamoto, T.; Ogura, T.; Terai, M.; Watanabe, H.; Watanabe, H.; Ikarashi, N.; Miyamura, M.; Tatsumi, T.; Saitoh, M.; Morioka, A.; Watanabe, K.; Saito, Y.; Yabe, Y.; Ikarashi, T.; Masuzaki, K.; Mochizuki, Y.; Mogami, T.)
Abstract	For 90 nm node poly-Si gated MISFETs with HfSiO (1.8 nm) insulator, a nearly symmetrical set of Vths for NFET and PFET: (0.38 V and -0.46 V, respectively) have been realized for low power device operation. The key technology is the suppression of Vth instability in PFETs arising from oxidation of the poly-Si/HfSiO interface, combined with channel engineering for the PFET. Our poly-Si/HfSiO gate-stacked CMOSFETs realize low I/sub off/ (N/PFET: 4.8/3.6 pA//spl mu/m) and high I/sub on/ (N/PFET: 469/140 /spl mu/A//spl mu/m) at V/sub DD/=1.2 V. Further, for SRAM cell using this CMOS, normal operation has been achieved.
File Size	289208
File Format	PDF
ISBN	0780378725
DOI	10.1109/IEDM.2003.1269362
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-12-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Manufacturing FETs Electrodes MISFETs Insulation CMOS technology Oxidation Power engineering and energy CMOSFETs Random access memory
Content Type	Text
Resource Type	Article

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