NDLI: Modeling metal dishing for interconnect optimization

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Ambient intelligence - key technologies in the information age

Requirements and strategies for semiconductor technologies for mobile communication terminals

Nano transformations: a future of our making

Fully working 1.25 /spl mu/m/sup 2/ 6T-SRAM cell with 45 nm gate length triple gate transistors

Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)

Double raised source/drain transistor with 50 nm gate length on 17 nm UTF-SOI for 1.1 /spl mu/m/sup 2/ embedded SRAM technology

Impact of actively body-bias controlled (ABC) SOI SRAM by using direct body contact technology for low-voltage application

A 90 nm CMOS MS/RF based foundry SOC technology comprising superb 185 GHz f/sub T/ RFMOS and versatile, high-Q passive components for cost/performance optimization

Device properties in 90 nm and beyond and implications on circuit design

Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs

Fully-depleted strained-Si on insulator NMOSFETs without relaxed SiGe buffers

Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs

Substrate-strained silicon technology: process integration [CMOS technology]

Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology

Comprehensive low-frequency and RF noise characteristics in strained-Si NMOSFETs

Process-strained Si (PSS) CMOS technology featuring 3D strain engineering

High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

ALD HfO/sub 2/ using heavy water (D/sub 2/O) for improved MOSFET stability

The impact of sub monolayers of HfO/sub 2/ on the device performance of high-k based transistors [MOSFETs]

Problems with metal-oxide high-/spl kappa/ dielectrics due to 1/t dielectric relaxation current in amorphous materials

High-k dielectrics and MOSFET characteristics

Thermally robust high quality HfN/HfO/sub 2/ gate stack for advanced CMOS devices

Nitrogen profile control by plasma nitridation technique for poly-Si gate HfSiON CMOSFET with excellent interface property and ultra-low leakage current

Effect of Hf-N bond on properties of thermally stable amorphous HfSiON and applicability of this material to sub-50nm technology node LSIs

SiGe HBT and BiCMOS technologies

A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs

SiGe:C BiCMOS technology with 3.6 ps gate delay

Ultra low power SiGe:C HBT for 0.18 /spl mu/m RF-BiCMOS

Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm gate CMOS

New method for temperature-dependent thermal resistance and capacitance accurate extraction in high-voltage DMOS transistors

Novel self-assembled ultra-low-k porous silica films with high mechanical strength for 45 nm BEOL technology

A new plasma-enhanced co-polymerization (PCP) technology for reinforcing mechanical properties of organic silica low-k/Cu interconnects on 300 mm wafers

Bottom-up fill of copper in high aspect ratio via holes by electroless plating

Low-pressure CMP for 300-mm ultra low-k (k=1.6-1.8)/Cu integration

Experimental and Monte Carlo analysis of drain-avalanche hot-hole injection for reliability optimization in Flash memories

A new statistical model to extract the stress induced oxide trap number and the probability density distribution of the gate current produced by a single trap

Statistical simulations to inspect and predict data retention and program disturbs in flash memories

Reliability models of data retention and read-disturb in 2-bit nitride storage flash memory cells

Novel operation schemes to improve device reliability in a localized trapping storage SONOS-type flash memory

Reliability study of CMOS FinFETs

RF performance vulnerability to hot carrier stress and consequent breakdown in low power 90 nm RFCMOS

An investigation of the damage mechanisms in impact ionization-induced "mixed-mode" reliability stressing of scaled SiGe HBTs

Organic semiconductor RFID transponders

Molecular thin film transistors with a subthreshold swing of 100 mV/decade

Organic transistors on fiber: a first step towards electronic textiles

Integration of organic field-effect transistors and rubbery pressure sensors for artificial skin applications

Fabrication of pentacene organic field-effect transistors containing SiO/sub 2/ nanoparticle thin film as the gate dielectric

Self-aligned top and bottom metal double gate low temperature poly-Si TFT fabricated at 550/spl deg/C on non-alkali glass substrate by using DPSS CW laser lateral crystallization method

Poly-Si TFT fabricated at 150/spl deg/C using ICP-CVD and excimer laser annealing for plastic substrates

Experimental evidence of grain-boundary related hot-carrier degradation mechanism in low-temperature poly-Si thin-film-transistors

2D QM simulation and optimization of decanano non-overlapped MOS devices

Atomistic tight-binding calculations for the investigation of transport in extremely scaled SOI transistors

Tunnel current measurements on P/N junction diodes and implications for future device design

Impact of the lateral source/drain abruptness on MOSFET characteristics and transport properties

Atomistic 3D process/device simulation considering gate line-edge roughness and poly-Si random crystal orientation effects [MOSFETs]

A model for Al/sub 2/O/sub 3/ ALD conformity and deposition rate from oxygen precursor reactivity

Modeling metal dishing for interconnect optimization

Current status of the phase change memory and its future

Organic materials for high-density non-volatile memory applications

Recent progress in FET-type ferroelectric memories

Highly scalable and CMOS-compatible STTM cell technology

Few electron memories: finding the compromise between performance, variability and manufacturability at the nano-scale

Taking SOI substrates and low-k dielectrics into high-volume microprocessor production

A robust 65-nm node CMOS technology for wide-range Vdd operation

A 65 nm CMOS technology with a high-performance and low-leakage transistor, a 0.55 /spl mu/m/sup 2/ 6T-SRAM cell and robust hybrid-ULK/Cu interconnects for mobile multimedia applications

Soft error immune 0.46 /spl mu/m/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM

Semiconductor spintronics: manipulating electron and nuclear spins

Monolithic vertical integration of Si/SiGe HBT and Si-based resonant interband tunneling diode demonstrating latching operation and adjustable peak-to-valley current ratios

Nanowires as building blocks for nanoelectronics and nanophotonics

Fermi level pinning with sub-monolayer MeOx and metal gates [MOSFETs]

Performance comparison of sub 1 nm sputtered TiN/HfO/sub 2/ nMOS and pMOSFETs

Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)

Fully silicided NiSi and germanided NiGe dual gates on SiO/sub 2//Si and Al/sub 2/O/sub 3//Ge-on-insulator MOSFETs

Compatibility of dual metal gate electrodes with high-k dielectrics for CMOS

Performance improvement of MOSFET with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric and CVD-TaN metal gate deposited by TAIMATA

Towards microscopic understanding of MOSFET reliability: the role of carrier energy and transport simulations

A new observation of enhanced bias temperature instability in thin gate oxide p-MOSFETs

Universal recovery behavior of negative bias temperature instability [PMOSFETs]

A critical examination of the mechanics of dynamic NBTI for PMOSFETs

NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs]

Effect of pMOST bias-temperature instability on circuit reliability performance

Record efficiency and gain at 2.1 GHz of high power RF transistors for cellular and 3G base stations

The impact of substrate surface potential on the performance of RF power LDMOSFETs on high-resistivity SOI

Highly manufacturable 40-50 GHz VCOs in a 120 nm system-on-chip SOI technology

Substrate transfer: enabling technology for RF applications

RF passive devices on Si with excellent performance close to ideal devices designed by electro-magnetic simulation

High performance ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors for RF and mixed signal IC applications

GaN based high brightness LEDs and UV LEDs

Color filtering metallization for optoelectronic 100nm CMOS circuits

Drastically reduced dark current by pulse-time-modulated plasma for precise micro lens fabrication in highly sensitive CCD image sensor

All-ITO gate, two-phase CCD image sensor technology

Air-gap guard ring for pixel sensitivity and crosstalk improvement in deep sub-micron CMOS image sensor

Fin-channel-array transistor (FCAT) featuring sub-70nm low power and high performance DRAM

An outstanding and highly manufacturable 80nm DRAM technology

A novel W/WNx/dual-gate CMOS technology for future high-speed DRAM having enhanced retention time and reliability

A simple and high-performance 130 nm SOI eDRAM technology using floating-body pass-gate transistor in trench-capacitor cell for system-on-a-chip (SoC) applications

Fully compatible integration of high density embedded DRAM with 65nm CMOS technology (CMOS5)

Optimized strained Si/strained Ge dual-channel heterostructures for high mobility P- and N-MOSFETs

Epitaxial strained germanium p-MOSFETs with HfO/sub 2/ gate dielectric and TaN gate electrode

A germanium NMOSFET process integrating metal gate and improved hi-/spl kappa/ dielectrics

Issues in NiSi-gated FDSOI device integration

Locally strained ultra-thin channel 25nm narrow FDSOI devices with metal gate and mesa isolation

Highly performant double gate MOSFET realized with SON process

High performance CMOS fabricated on hybrid substrate with different crystal orientations

Re-investigation of MOS inversion layer mobility from non-universality and possible new scattering mechanism aspects

Quantitative assessment of mobility degradation by remote Coulomb scattering in ultra-thin oxide MOSFETs: measurements and simulations

Simulation of quantum electronic transport in small devices: a master equation approach

Assessment of Ge n-MOSFETs by quantum simulation

Investigation of scaling methodology for strained Si n-MOSFETs using a calibrated transport model

20 nm N/sup +/ abrupt junction formation in strained Si/Si/sub 1-x/Ge/sub x/ MOS device

Fluorine implantation impact in extension region on the electrical performance of sub-50nm P-MOSFETs

Dopant redistribution effects in preamorphized silicon during low temperature annealing

Self-limiting laser thermal process for ultra-shallow junction formation of 50-nm gate CMOS

Low resistivity nickel germanosilicide contacts to ultra-shallow Si/sub 1-x/Ge/sub x/ source/drain junctions for nanoscale CMOS

CVD-cobalt for the next generation of source/drain salicidation and contact silicidation in novel MOS device structures with complex shape

Technology scaling effects on the ESD design parameters in sub-100 nm CMOS transistors

Implementation of temperature dependent contact resistance model for the analysis of deep submicron devices under ESD

Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides

Characterization of multi-bit soft error events in advanced SRAMs

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation

Integration and reliability issues of Cu/SiOC interconnect for ArF/90 nm node SoC manufacturing

Alleviating electromigration through re-engineering the interface between Cu & dielectric-diffusion-barrier in 90 nm Cu/SiOC (k=2.9) device

Hybrid silicon/molecular memories: co-engineering for novel functionality

Low voltage, scalable nanocrystal flash memory fabricated by templated self assembly

High speed and nonvolatile Si nanocrystal memory for scaled flash technology using highly field-sensitive tunnel barrier

Program/erase dynamics and channel conduction in nanocrystal memories

New non-volatile memory with extremely high density metal nano-dots

Operational and reliability comparison of discrete-storage nonvolatile memories: advantages of single- and double-layer metal nanocrystals

12 W/mm recessed-gate AlGaN/GaN heterojunction field-plate FET

AlGaN/GaN HEMTs on SiC: towards power operation at V-band

Layer design for GaAs-based DHBTs enabling 28 V high-power microwave applications

Multifunction integration of junction-MOSFETs and nonvolatile FETs on a single 4H-SiC substrate for 300/spl deg/C operation

3.5-watt AlGaN/GaN HEMTs and amplifiers at 35 GHz

A high power Tx/Rx switch IC using AlGaN/GaN HFETs

600V AlGaN/GaN power-HEMT: design, fabrication and demonstration on high voltage DC-DC converter

How far will silicon nanocrystals push the scaling limits of NVMs technologies?

A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory

Integration of fluorinated nano-crystal memory cells with 4.6F/sup 2/ size by landing plug polysilicon contact and direct-tungsten bitline

FinFET SONOS flash memory for embedded applications

A novel SONOS structure of SiO/sub 2//SiN/Al/sub 2/O/sub 3/ with TaN metal gate for multi-giga bit flash memories

A novel leakage current separation technique in a direct tunneling regime gate oxide SONOS memory cell

High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs

A 65nm node strained SOI technology with slim spacer

Device design considerations for ultra-thin SOI MOSFETs

High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering

A highly manufacturable low power and high speed HfSiO CMOS FET with dual poly-Si gate electrodes

Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform

Ultra-low thermal budget CMOS process for 65nm-node low-operation-power applications

High mobility Si/SiGe strained channel MOS transistors with HfO/sub 2//TiN gate stack

Atomic-layer-deposited ultrathin Si-nitride gate dielectrics - a better choice for sub-tunneling gate dielectrics

New approaches to improve the endurance of TiN/HfO/sub 2//TiN capacitor during the back-end process for 70nm DRAM device

A fourth material: thermally stable organic gap-fill spin-on-polymer enabling new integration concepts [DRAM example]

A novel graded antireflective coating with built-in hardmask properties enabling 65nm and below CMOS device patterning

The integration of proton bombardment process into the manufacturing of mixed-signal/RF chips

Physical insights on design and modeling of nanoscale FinFETs

3-D Monte Carlo simulations of FinFETs

A novel, very high performance, sub-20nm depletion-mode double-gate (DMDG) Si/Si/sub x/Ge/sub (1-x)//Si channel PMOSFET

Investigation of performance limits of germanium double-gated MOSFETs

A computational study of ballistic silicon nanowire transistors

Scaling analysis of phase-change memory technology

SETMOS: a novel true hybrid SET-CMOS high current Coulomb blockade oscillation cell for future nano-scale analog ICs

Super-scaled InP HBTs for 150 GHz circuits

Breakdown voltage limitations, impact ionization, and interband tunneling in InP/GaAsSb/InP type-II NpN DHBTs

Electrical degradation mechanisms of RF power GaAs PHEMTs

Performance enhancement of 0.13/spl mu/m In/sub 0.65/GaAs PHEMT by reduction of parasitic effect using novel double-deck shaped (DDS) gate structure

Improvement of circuit-speed of HEMTs IC by reducing the parasitic capacitance

High frequency InAs-channel HEMTs for low power ICs

Vertical multi-RESURF MOSFETs exhibiting record low specific resistance

Advancements in complementary carbon nanotube field-effect transistors

Narrow-channel-MOSFET having Si-dots for high-rate generation of random numbers

Wafer scale biomolecule grafting: the first step for low cost, high throughput active biochip manufacturing

Room-temperature operation of highly functional single-electron transistor logic based on quantum mechanical effect in ultra-small silicon dot

A high density, low on-resistance 700V class trench offset drain LDMOSFET (TOD-LDMOS)

Thousands of microcantilevers for highly parallel and ultra-dense data storage

The detection of DNA using a silicon nanopore

High sensitive structure and its fabrication process for MEMS fingerprint sensor to various fingers

Closed-loop cooling technologies for microprocessors

Electrowetting-based on-chip sample processing for integrated microfluidics

Single crystal SiC capacitive pressure sensor at 400/spl deg/C

Device physics at the scaling limit: what matters? [MOSFETs]

Inversion channel mobility in high-/spl kappa/ high performance MOSFETs

Unified mobility model for high-/spl kappa/ gate stacks [MISFETs]

Low noise balanced-CMOS on Si(110) surface for analog/digital mixed signal circuits

Experimental study on carrier transport mechanisms in double- and single-gate ultrathin-body MOSFETs - Coulomb scattering, volume inversion, and /spl delta/T/sub SOI/-induced scattering

Physical mechanism for high hole mobility in [110]-surface strained- and unstrained-MOSFETs

Impact ionization in strained-Si/SiGe heterostructures

70nm NAND flash technology with 0.025 /spl mu/m/sup 2/ cell size for 4Gb flash memory

90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F/sup 2//bit and programming throughput of 10 MB/s

An 8F/sup 2/ MRAM technology using modified metal lines

MRAM with lamellar structure as free layer

Noble FeRAM technologies with MTP cell structure and BLT ferroelectric capacitors

Process roadmap and challenges for metal barriers [copper interconnects]

A 65nm-node, Cu interconnect technology using porous SiOCH film (k=2.5) covered with ultra-thin, low-k pore seal (k=2.7)

High performance 90/65nm BEOL technology with CVD porous low-k dielectrics (k/spl sim/2.5) and low-k etching stop (k/spl sim/3.0)

Misalignment-tolerated, Cu dual damascene interconnects with low-k SiOCH film by a novel via-first, multi-hard-mask process for sub-100nm-node, ASICs

Robust porous MSQ (k=2.3, e=12 GPa) for low-temperature (<350/spl deg/C) Cu/low-k integration using ArF resist mask process

Reemergence of the surface-potential-based compact MOSFET models

New compact model for induced gate current noise [MOSFET]

Hydrodynamic modeling of RF noise in CMOS devices

Predictive spiral inductor compact model for frequency and time domain

Voltage and temperature dependence of capacitance of high-k HfO/sub 2/ MIM capacitors: a unified understanding and prediction

Thermal analysis of ultra-thin body device scaling [SOI and FinFet devices]

A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management

Writing current reduction for high-density phase-change RAM

A GeSbTe phase-change memory cell featuring a tungsten heater electrode for low-power, highly stable, and short-read-cycle operations

Novel cell structure of PRAM with thin metal layer inserted GeSbTe

An access-transistor-free (0T/1R) non-volatile resistance random access memory (RRAM) using a novel threshold switching, self-rectifying chalcogenide device

Scaled 2bit/cell SONOS type nonvolatile memory technology for sub-90nm embedded application using SiN sidewall trapping structure

A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory

Critical assessment of soft breakdown stability time and the implementation of new post-breakdown methodology for ultra-thin gate oxides [MOSFET]

Reliability issues for high-k gate dielectrics

Analysis of charge trapping and breakdown mechanism in high-k dielectrics with metal gate electrode using carrier separation

Degradation mechanism of HfSiON gate insulator and effect of nitrogen composition on the statistical distribution of the breakdown

Effect of bulk trap density on HfO/sub 2/ reliability and yield

Characterization and comparison of the charge trapping in HfSiON and HfO/sub 2/ gate dielectrics

Improvement of NBTI and electrical characteristics by ozone pre-treatment and PBTI issues in HfAlO(N) high-k gate dielectrics

Integrated sensor and electronics processing for >10^8 "iMEMS" inertial measurement unit components

UHF micromechanical extensional wine-glass mode ring resonators

High frequency micromechanical piezo-on-silicon block resonators

Series-resonant micromechanical resonator oscillator

Novel fabrication process and structure of a low-voltage-operation micromirror array for optical MEMS switches

A new isolation method for single crystal silicon MEMS and its application to z-axis microgyroscope

Mixed-signal performance of sub-100nm fully-depleted SOI devices with metal gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions

A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

High performance GaN HEMTs at 40 GHz with power density of 2.8W/mm

A 174 W high-efficiency GaN HEMT power amplifier for W-CDMA base station applications

Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel

Sub-10-nm planar-bulk-CMOS devices using lateral junction control

Biochemical sensors based on bulk acoustic wave resonators

A 0.18 /spl mu/m 4Mb toggling MRAM

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Modeling metal dishing for interconnect optimization

Content Provider	IEEE Xplore Digital Library
Author	Runzi Chang Yu Cao Spanos, C.J.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA (Runzi Chang; Yu Cao; Spanos, C.J.)
Abstract	An analytical dishing model is developed for the damascene process, based on experimental data and physical analysis. A study utilizing this model shows that the impact of dishing on performance can be mitigated at both the process and design stages. More specifically, process improvement is favorable when the dishing radius is less than 50 /spl mu/m. During design, dishing effects can be suppressed by uniformly splitting a wide line into several narrower lines; the most beneficial number of line-splitting is 2-4 from both efficiency and performance considerations.
File Size	319076
File Format	PDF
ISBN	0780378725
DOI	10.1109/IEDM.2003.1269267
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-12-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit interconnections Testing Dielectrics Electrical resistance measurement Surface resistance Semiconductor device measurement Analytical models Copper Chemical technology Shape measurement
Content Type	Text
Resource Type	Article

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