NDLI: NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes

Content Provider	IEEE Xplore Digital Library
Author	Kukner, H. Weckx, P. Morrison, S. Raghavan, P. Kaczer, B. Catthoor, F. Van Der Perre, L. Lauwereins, R. Groeseneken, G.
Copyright Year	2014
Description	Author affiliation: imec vzw, Leuven, Belgium (Kukner, H.; Weckx, P.; Morrison, S.; Raghavan, P.; Kaczer, B.; Catthoor, F.; Van Der Perre, L.; Lauwereins, R.; Groeseneken, G.)
Abstract	Reliability of advanced deeply scaled CMOS technologies is being threatened by time-dependent degradation mechanisms such as Negative Bias Temperature Instability (NBTI) phenomenon that cause workload-dependent shifts on a transistor's threshold voltage (VTH), and performance during its lifetime. In this study, NBTI-induced performance degradation of 32-bit adders (one of the most fundamental block of a processor's arithmetic logic unit) is investigated from the points of architectural topology, technology scaling (i.e. commercial 28, 45, 65nm nodes) and workload dependency. The selected adder architectures vary from basic to complex parallel-prefix ones. A workload-dependent, NBTI aging-aware digital design flow was developed within the industry standard EDA tool chain. NBTI model is based on the extracted Capture and Emission Time (CET) maps from the actual wafer measurements. Static Timing Analysis (STA) is performed to evaluate the performance degradation at the +3σ corner. Results on adders under the NBTI aging after 3 years show a performance loss up to 16%. NBTI aging results in the replacement of the time-zero critical path by an initially non-critical path during a circuit's lifetime. The time-zero critical path can shift to a new one with a probability of 89%. Technology scaling and the choice of process technology can impact the degradation by 2×. Finally, the performance degradation can vary up to 8.2× under workload variations.
Starting Page	98
Ending Page	107
File Size	424615
Page Count	10
File Format	PDF
ISBN	9781479957934
DOI	10.1109/DSD.2014.82
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-27
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Aging Integrated circuit modeling Logic gates Adders Degradation Computational modeling Stress library characterization Bias Temperature Instability reliability aging adder planar FET scaling
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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