NDLI: Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures

Content Provider	IEEE Xplore Digital Library
Author	Sousa, E. Gangadharan, D. Hannig, F. Teich, J.
Copyright Year	2014
Description	Author affiliation: Dept. of Comput. Sci., Friedrich-Alexander-Univ. Erlangen-Nurnberg (FAU), Erlangen, Germany (Sousa, E.; Gangadharan, D.; Hannig, F.; Teich, J.)
Abstract	This paper describes a runtime reconfigurable bus arbitration technique for concurrent applications on heterogeneous MPSoC architectures. Here, a hardware/software approach is introduced as part of a runtime framework that enables selecting and adapting different policies (i. e., fixed-priority, TDMA, and Round-Robin) such that the performance goals of concurrent applications can be satisfied. To evaluate the hardware cost, we compare our proposed solution with respect to a well-known SPARC V8 architecture supporting fixed-priority arbitration. Notably, even providing the flexibility for selecting up to three different policies, our reconfigurable arbiter needs only 25% and 7% more LUTs and slices registers, respectively. The reconfiguration overhead for changing between different policies is 56 cycles and for programming new time slots, only 28 cycles are necessary. For demonstrating the benefits of this reconfiguration framework, we setup a mixed hard/soft real-time scenario by considering four applications with different timeliness requirements. The experimental results show that by reconfiguring the arbiter, less processing elements can be used for achieving a specific target frame rate. Moreover, adjusting the time slots for TDMA, we can speedup a soft real-time algorithm while still satisfying the deadline for hard real-time applications.
Starting Page	74
Ending Page	81
File Size	452102
Page Count	8
File Format	PDF
ISBN	9781479957934
DOI	10.1109/DSD.2014.105
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-27
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Software Time division multiple access Computer architecture Runtime System-on-chip Real-time systems Heterogeneous MPSoC Architectures Reconfigurable Bus Arbitration Concurrent Applications
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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