NDLI: Seesaw: An Area-Optimized FPGA Viterbi Decoder for PUFs

Content Provider	IEEE Xplore Digital Library
Author	Hiller, M. Lima, L.R. Sigl, G.
Copyright Year	2014
Description	Author affiliation: Inst. for Security in Inf. Technol., Tech. Univ. Munchen, Munich, Germany (Hiller, M.; Lima, L.R.; Sigl, G.)
Abstract	Physical Unclonable Functions PUFs are popular security primitives to provide cryptographic keys on FPGAs. However, PUFs require error correction to create reliable cryptographic keys. This work presents a highly optimized Viterbi decoder, adapted to the constraints of PUFs on FPGAs, primarily area but also low power. Our Seesaw architecture contains two block RAMs that are connected through a custom low-area data path. As main result, alternating data access patterns reduce the complexity of the data handling in the Viterbi decoder. Instead of translating through the entire trellis, we introduce a method that only operates on the last state. The new access pattern permits to store the intermediate results in block RAM and leads to a compact overall footprint with low register count. Synthesis results for one legacy and one state-of-the art FPGA, and a comparison to state-of-the-art implementations demonstrate the efficiency of our new Seesaw architecture. Our decoder requires only 65 FPGA slices and 2 block RAMs to carry out the entire Viterbi decoding for a popular (2, 1, [7]) convolutional code.
Starting Page	387
Ending Page	393
File Size	213718
Page Count	7
File Format	PDF
ISBN	9781479957934
DOI	10.1109/DSD.2014.33
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-27
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Field programmable gate arrays Decoding Convolutional codes Viterbi algorithm Computer architecture Registers FPGA Physical Unclonable Functions (PUFs) Error Correction Convolutional Code Viterbi Algorithm VLSI
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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