NDLI: End-to-End Real-Time Communication in Mixed-Criticality Systems Based on Networked Multicore Chips

Content Provider	IEEE Xplore Digital Library
Author	Obermaisser, R. Owda, Z. Abuteir, M. Ahmadian, H. Weber, D.
Copyright Year	2014
Description	Author affiliation: Univ. of Siegen, Siegen, Germany (Obermaisser, R.; Owda, Z.; Abuteir, M.; Ahmadian, H.; Weber, D.)
Abstract	Mixed-criticality systems combine applications at different levels of criticality on the same platform. Today, mixed-criticality integration is addressed individually at different integration levels such as the operating system, the chip-level and the cluster-level. Since many mixed-criticality systems span all of these integration levels, a system perspective of mixed-criticality applications is required. The access to remote resources located on another chip needs to be relayed via gateways involving gateways between on-chip and off-chip networks (i.e., vertical integration) and gateways between different types of off-chip networks (i.e., horizontal integration). This paper introduces a system model with gateways for end-to-end channels over hierarchical, heterogeneous and mixed-criticality networks. We focus on the timing of end-to-end channels, as well as the interoperability across gateways.
Starting Page	293
Ending Page	302
File Size	261794
Page Count	10
File Format	PDF
ISBN	9781479957934
DOI	10.1109/DSD.2014.34
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-27
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delays Nickel Routing Logic gates Aerospace electronics Receivers time-triggered end-to-end communication mixed-criticality systems multicore chip off-chip communication on-chip communication gateway rate-constrained
Content Type	Text
Resource Type	Article

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