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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jinjun Xiong Kingho Tam Lei He |
| Copyright Year | 2005 |
| Description | Author affiliation: Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA (Jinjun Xiong; Kingho Tam; Lei He) |
| Abstract | A comprehensive probabilistic methodology is proposed to solve the buffer insertion problem with the consideration of process variations. In contrast to a recent work, we point out, for the first time, that the correlation between the required arrival time and the downstream loading capacitance must be considered in order to solve the problem "correctly". We develop an efficient bottom-up recursive algorithm to calculate the joint probability density function that accurately captures the above correlation, and propose effective pruning rules to exclude probabilistically inferior solutions. We verify our buffer insertion using timing analysis with both device and interconnect variations, and show that compared to the conventional buffer insertion algorithm using nominal device and interconnect parameters, our new buffer insertion methodology can reduce the probability of timing violation by up to 30%. |
| Sponsorship | European Design and Autom. Assoc. EDA Consortium IEEE Comput. Soc. TTTC, IEEE Comput. Soc. DATC, ECSI, ACM SIGDA, RAS |
| Starting Page | 970 |
| Ending Page | 975 |
| File Size | 229636 |
| Page Count | 6 |
| File Format | |
| ISBN | 0769522882 |
| ISSN | 15301591 |
| DOI | 10.1109/DATE.2005.85 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-03-07 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Capacitance Timing Routing Integrated circuit interconnections Probability density function Distributed computing Wire Building integrated photovoltaics Law Legal factors |
| Content Type | Text |
| Resource Type | Article |
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