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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Takach, A. Bowyer, B. Bollaert, T. |
| Copyright Year | 2005 |
| Description | Author affiliation: Mentor Graphics Corp., Beaverton, OR, USA (Takach, A.; Bowyer, B.; Bollaert, T.) |
| Abstract | The algorithms used in wireless applications are increasingly more sophisticated and consequently more challenging to implement in hardware. Traditional design flows require developing the micro architecture, coding the RTL, and verifying the generated RTL against the original functional C or MATLAB specification. This paper describes a C-based design flow that is well suited for the hardware implementation of DSP algorithms commonly found in wireless applications. The C design low relies on guided synthesis to generate the RTL directly from the untimed C algorithm. The specifics of the C-based design flow are described using a simple DSP filtering algorithm consisting of a forward adaptive equalizer, a 64-QAM slicer and an adaptive decision feedback equalizer. The example illustrates some of the capabilities and advantages offered by this flow. |
| Sponsorship | European Design and Autom. Assoc. EDA Consortium IEEE Comput. Soc. TTTC, IEEE Comput. Soc. DATC, ECSI, ACM SIGDA, RAS |
| Starting Page | 124 |
| Ending Page | 129 |
| File Size | 127349 |
| Page Count | 6 |
| File Format | |
| ISBN | 0769522882 |
| ISSN | 15301591 |
| DOI | 10.1109/DATE.2005.87 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-03-07 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Algorithm design and analysis MATLAB Mathematical model Digital signal processing Graphics Field programmable gate arrays Wireless communication Delay Floating-point arithmetic |
| Content Type | Text |
| Resource Type | Article |
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