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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Galanis, M.D. Milidonis, A. Theodoridis, G. Soudris, D. Goutis, C.E. |
| Copyright Year | 2005 |
| Description | Author affiliation: Electr. & Comput. Eng. Dept., Univ. of Patras, Rio, Greece (Galanis, M.D.; Milidonis, A.) |
| Abstract | In this paper, we propose a methodology for partitioning and mapping computational intensive applications in reconfigurable hardware blocks of different granularity. A generic hybrid reconfigurable architecture is considered so as the methodology can be applicable to a large number of heterogeneous reconfigurable platforms. The methodology mainly consists of two stages, the analysis and the mapping of the application onto fine and coarse-grain hardware resources. A prototype framework consisting of analysis, partitioning and mapping tools has been also developed. For the coarse-grain reconfigurable hardware, we use our previously developed high-performance coarse-grain datapath. In this work, the methodology is validated using two real-world applications, an OFDM transmitter and a JPEG encoder. In the case of the OFDM transmitter, a maximum clock cycle decrease of 82 % relative to the ones in an all fine-grain mapping solution is achieved. The corresponding performance improvement for the JPEG is 43 %. |
| Sponsorship | European Design and Autom. Assoc. EDA Consortium IEEE Comput. Soc. TTTC, IEEE Comput. Soc. DATC, ECSI, ACM SIGDA, RAS |
| Starting Page | 247 |
| Ending Page | 252 |
| File Size | 138878 |
| Page Count | 6 |
| File Format | |
| ISBN | 0769522882 |
| ISSN | 15301591 |
| DOI | 10.1109/DATE.2005.29 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-03-07 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Acceleration Hardware Application software Physics computing OFDM Transmitters Field programmable gate arrays Very large scale integration Computer applications Reconfigurable architectures |
| Content Type | Text |
| Resource Type | Article |
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