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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Vorwerk, K. Kennings, A. |
| Copyright Year | 2005 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada (Vorwerk, K.; Kennings, A.) |
| Abstract | One of the greatest impediments to achieving high quality placements using force-directed methods lies in the large amount of overlap initially present in these techniques. This overlap makes the determination of cell ordering difficult and can lead to the inadvertent separation of highly connected cells by the spreading forces. We show that a multi-level clustering strategy can minimize the ill effects of overlap and improve the quality of placements generated by the force-directed tool FDP. Moreover, we present a means of improving initial cell ordering through the unification of min-cut partitioning and force-based placement, and describe an enhanced median improvement heuristic which further aids in minimizing HPWL. Numerical results are presented showing that our flow generates placements which are, on average, 15% better than mPG and 4% better than Capo 9.0 on mixed-size designs. |
| Sponsorship | European Design and Autom. Assoc. EDA Consortium IEEE Comput. Soc. TTTC, IEEE Comput. Soc. DATC, ECSI, ACM SIGDA, RAS |
| Starting Page | 902 |
| Ending Page | 907 |
| File Size | 258306 |
| Page Count | 6 |
| File Format | |
| ISBN | 0769522882 |
| ISSN | 15301591 |
| DOI | 10.1109/DATE.2005.59 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-03-07 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Vectors Wire Simulated annealing Circuits Impedance Analytical models Councils Runtime Open source software Minimization |
| Content Type | Text |
| Resource Type | Article |
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