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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ruiz-Sautua, R. Molina, M.C. Mendias, J.M. Hermida, R. |
| Copyright Year | 2005 |
| Description | Author affiliation: Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain (Ruiz-Sautua, R.; Molina, M.C.; Mendias, J.M.; Hermida, R.) |
| Abstract | Early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the slowest operation. This resulted in large slack times wasted in those cycles executing faster operations. To reduce the wasted times multi-cycle and chaining techniques have been employed. While these techniques have produced successful designs, their effectiveness are often limited due to the area increment that may derive from chaining, and the extra latencies that may derive from multicycling. In this paper we present an optimization method that solves the time-constrained scheduling problem by transforming behavioural specifications into new ones whose subsequent synthesis substantially improves circuit performance. Our proposal breaks up some of the specification operations, allowing their execution during several possibly unconsecutive cycles, and also the calculation of several data-dependent operation fragments in the same cycle. To do so, it takes into account the circuit latency and the execution time of every specification operation. The experimental results carried out show that circuits obtained from the optimized specification are on average 60% faster than those synthesized from the original specification, with only slight increments in the circuit area. |
| Sponsorship | European Design and Autom. Assoc. EDA Consortium IEEE Comput. Soc. TTTC, IEEE Comput. Soc. DATC, ECSI, ACM SIGDA, RAS |
| Starting Page | 1252 |
| Ending Page | 1257 |
| File Size | 266983 |
| Page Count | 6 |
| File Format | |
| ISBN | 0769522882 |
| ISSN | 15301591 |
| DOI | 10.1109/DATE.2005.81 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-03-07 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Circuit optimization High level synthesis Clocks Delay Scheduling algorithm Circuit synthesis Routing Processor scheduling Circuit testing Optimization methods |
| Content Type | Text |
| Resource Type | Article |
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