NDLI: A generic micro-architectural test plan approach for microprocessor verification

Content Provider	IEEE Xplore Digital Library
Author	Adir, A. Azatchi, H. Bin, E. Peled, O. Shoikhet, K.
Copyright Year	2005
Description	Author affiliation: IBM Res. Lab., Haifa Univ., Israel (Adir, A.; Azatchi, H.; Bin, E.; Peled, O.; Shoikhet, K.)
Abstract	Modern microprocessors share several common types of micro-architectural building blocks. The rising complexity of the micro-architecture increases the risk of bugs and the difficulty of achieving comprehensive verification. We propose a methodology to exploit the commonality in the different microprocessors to create a design-independent micro-architectural test plan. Our method allows the testing of the huge micro-architectural test space by using systematic partitioning, which offers a high level of comprehensiveness of the tested behaviors. We show how this method was used to find bugs during verification of an actual high-end microprocessor. Our results show the advantages of this approach over the more traditional test methods that use design specific test plans or that use tools with little micro-architectural knowledge for covering micro-architectural aspects of the design.
Sponsorship	acm Special Interest Group on design automation (SIGda) EDA Consortium IEEE CASS/CANDE IEEE Circuits & Syst. Soc
Starting Page	769
Ending Page	774
File Size	1200431
Page Count	6
File Format	PDF
ISBN	1595930582
DOI	10.1109/DAC.2005.193919
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Microprocessors Computer bugs System testing Logic testing Pipelines Permission Laboratories Modems Design methodology Logic design
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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