NDLI: System-level energy-efficient dynamic task scheduling

Content Provider	IEEE Xplore Digital Library
Author	Jianli Zhuo Chakrabarti, C.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA (Jianli Zhuo; Chakrabarti, C.)
Abstract	Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time. But in a DVS system consisting of a DVS processor and multiple devices, slowing down the processor increases the device energy consumption and thereby the system-level energy consumption. In this paper, we present dynamic task scheduling algorithms for periodic tasks that minimize the system-level energy (CPU energy + device standby energy). The algorithms use a combination of (i) optimal speed setting, which is the speed that minimizes the system energy for a specific task, and (ii) limited preemption which reduces the numbers of possible preemptions. For the case when the CPU power and device power are comparable, these algorithms achieve up to 43% energy savings, but only up to 12% over the non-DVS scheduling. If the device power is large compared to the CPU power, we show that DVS should not be employed.
Sponsorship	acm Special Interest Group on design automation (SIGda) EDA Consortium IEEE CASS/CANDE IEEE Circuits & Syst. Soc
Starting Page	628
Ending Page	631
File Size	831668
Page Count	4
File Format	PDF
ISBN	1595930582
DOI	10.1109/DAC.2005.193887
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Energy efficiency Dynamic scheduling Voltage control Scheduling algorithm Energy consumption Processor scheduling Dynamic voltage scaling Permission Operating systems Energy management
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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