NDLI: N-detection under transparent-scan

Content Provider	IEEE Xplore Digital Library
Author	Pomeranz, I.
Copyright Year	2005
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA (Pomeranz, I.)
Abstract	We study the quality of test sequences under a test application scheme called transparent-scan as n-detection test sequences. We obtain transparent-scan sequences from combinational test sets. We show that for the same number of clock cycles required to apply a compact single-detection combinational test set, a transparent-scan sequence detects faults more times than the combinational test set. We note that a transparent-scan sequence based on a combinational test set contains unspecified values. We consider several procedures for specifying the unspecified values of the transparent-scan sequence, and study their effects. We also study the extension of a transparent-scan test sequence into an n-detection test sequence that detects every target fault at least n times.
Sponsorship	acm Special Interest Group on design automation (SIGda) EDA Consortium IEEE CASS/CANDE IEEE Circuits & Syst. Soc
Starting Page	129
Ending Page	134
File Size	1237966
Page Count	6
File Format	PDF
ISBN	1595930582
DOI	10.1109/DAC.2005.193786
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Circuit testing Clocks Compaction Fault detection Circuit faults Logic testing Permission Sequential circuits Sequential analysis Fault tolerance
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Fault Diagnosis under Transparent-Scan

Test Compaction for Transition Faults under Transparent-Scan

Test sequence compaction by reduced scan shift and retiming

Static test compaction for IDDQ testing of sequential circuits

Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences

Test sequence compaction for sequential circuits with reset states

Gate-delay fault test with conventional scan-design

A scan design for asynchronous sequential logic circuits using SR-latches

Observation time reduction for IDDQ testing of bridging faults in sequential circuits

N-detection under transparent-scan

Similar Documents

Fault Diagnosis under Transparent-Scan

Test Compaction for Transition Faults under Transparent-Scan

Test sequence compaction by reduced scan shift and retiming

Static test compaction for IDDQ testing of sequential circuits

Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences

Test sequence compaction for sequential circuits with reset states

Gate-delay fault test with conventional scan-design

A scan design for asynchronous sequential logic circuits using SR-latches

Observation time reduction for IDDQ testing of bridging faults in sequential circuits

N-detection under transparent-scan