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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | McCormick, M. Porath, P. |
| Copyright Year | 2015 |
| Description | Author affiliation: Implant Process Eng., ON Semicond., Pocatello, ID, USA (McCormick, M.; Porath, P.) |
| Abstract | While contamination of $BF_{2}^{+}$ implants by double charged molybdenum has been well documented, the impact of that contamination on antimony implants has not been investigated and is the subject of this study. Many advanced power processes incorporate buried p and n regions created by implanting the substrate prior to growing the final epitaxial silicon layer. One such process is our 0.35um 80V HV CMOS process used in this study. For n-type regions, either arsenic or antimony is typically implanted. Antimony has the advantage of lower diffusion coefficients and therefore less auto-doping issues during the epitaxial silicon process compared with arsenic. While low levels of molybdenum contamination during the antimony implant will not impact the process, it was found that higher levels of contamination, above 3.2 $×10^{11}$ $ions/cm^{2},$ can create both `mound' defects (Figure 2) and planar stacking faults (Figure 3) in the epitaxial silicon layer. For the specific process studied, the estimated yield impact is approximately 0.5%. |
| Starting Page | 167 |
| Ending Page | 168 |
| File Size | 108142 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781479999309 |
| DOI | 10.1109/ASMC.2015.7164462 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-05-03 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Contamination Implants Ions Stacking Epitaxial growth Silicon |
| Content Type | Text |
| Resource Type | Article |
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