NDLI: Shortening of cycle time in semiconductor manufacturing via meaningful lot sizes

Content Provider	IEEE Xplore Digital Library
Author	Eberts, D. Keil, S. Peipp, F. Lasch, R.
Copyright Year	2015
Description	Author affiliation: Fac. of Bus. & Econ., Dresden Univ. of Technol., Dresden, Germany (Keil, S.; Peipp, F.; Lasch, R.) \|\| Dept. of Line Control, Infineon Technol. Dresden GmbH, Dresden, Germany (Eberts, D.)
Abstract	Cycle time requirements from prime or major customers contradict the ever-increasing complexity of wafer fabrication. Lot size variations show up as significant cycle time improvement potential for single wafer processes. Further reduction potential aside of process times is shown regarding tool-internal waiting times. A model is elaborated to assure cost efficiency while significantly reducing lot raw tool time. The models innovation is to combine real lot move data with inside tool logistics to extend current research activities, including a simulation for its evaluation. Results of raw tool time reduction point to strategies for the surrounding WIP flow control.
Starting Page	34
Ending Page	41
File Size	329858
Page Count	8
File Format	PDF
ISBN	9781479999309
DOI	10.1109/ASMC.2015.7164447
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Mathematical model Semiconductor device modeling Data mining Complexity theory Logistics Throughput cost efficiency cycle time reduction time to market meaningful lot size raw tool time tool characteristics throughput prime customers
Content Type	Text
Resource Type	Article

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