NDLI: Determining schedules for reducing power consumption using multiple supply voltages

Content Provider	IEEE Xplore Digital Library
Author	Chabini, N. Aboulhamid, E.M. Savaria, Y.
Copyright Year	2001
Description	Author affiliation: LASSO, Univ. de Montreal, Que., Canada (Chabini, N.)
Abstract	Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply voltage of some computational elements in the circuit, with the penalty of an increase of their execution delay. To reduce the dynamic power consumption, without degrading the performance determined assuming that the circuit operates at the highest available supply voltage, the supply voltage of computational elements off critical paths can be scaled down. Defined here as MinP/sub dyn/, the problem of minimizing the dynamic power consumption, under performance constraints, by scaling down the supply voltage of computational elements on non-critical paths is NP-hard in general. Solving MinP/sub dyn/ for multi-phase clocked sequential circuits may allow to reduce their power consumption and the required number of registers. Reducing the number of registers also allows to reduce the power consumption, the number of control signals, and the area of the circuit. In this paper, we focus on devising methods to efficiently solve MinP/sub dyn/ for designs modeled as cyclic or acyclic graphs. More precisely, once the circuit is optimized for timing constraints, then we look for schedules that allow the computational elements of the circuit to operate at the lowest possible supply voltage. We present an integer linear programming formulation for that problem, which we use to devise a polynomial time solvable method and an exact algorithm based on a branch-and-bound technique. Experimental results confirm the effectiveness of the method and power reduction factors as high as 53.84% were obtained. Also, they show that the exact algorithm produces optimal results in a small number of tries, which is due to the rules used to prune useless solutions.
Sponsorship	IEEE Comput. Soc.
Starting Page	546
Ending Page	552
File Size	714022
Page Count	7
File Format	PDF
ISBN	0769512003
ISSN	10636404
DOI	10.1109/ICCD.2001.955089
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-09-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Dynamic voltage scaling Processor scheduling Registers Delay Degradation High performance computing Clocks Sequential circuits Constraint optimization
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Simultaneous Peak and Average Power Optimization in Synchronous Sequential Designs Using Retiming and Multiple Supply Voltages

An approach for reducing dynamic power consumption in synchronous sequential digital designs

Low Power and High Speed Multi Threshold Voltage Interface Circuits

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Power optimization in data-path scheduling and binding with multiple supply voltages and threshold voltages by simulated annealing

Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

Dynamic voltage and frequency scaling circuits with two supply voltages

Task Scheduling under Performance Constraints for Reducing the Energy Consumption of the GALS Multi-Processor SoC

Evaluating techniques for exploiting instruction slack

Determining schedules for reducing power consumption using multiple supply voltages

Similar Documents

Simultaneous Peak and Average Power Optimization in Synchronous Sequential Designs Using Retiming and Multiple Supply Voltages

An approach for reducing dynamic power consumption in synchronous sequential digital designs

Low Power and High Speed Multi Threshold Voltage Interface Circuits

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Power optimization in data-path scheduling and binding with multiple supply voltages and threshold voltages by simulated annealing

Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

Dynamic voltage and frequency scaling circuits with two supply voltages

Task Scheduling under Performance Constraints for Reducing the Energy Consumption of the GALS Multi-Processor SoC

Evaluating techniques for exploiting instruction slack

Determining schedules for reducing power consumption using multiple supply voltages