NDLI: Reducing cache pollution of prefetching in a small data cache

Content Provider	IEEE Xplore Digital Library
Author	Reungsang, P. Sun Kyu Park Seh-Woong Jeong Hyung-Lae Roh Gyungho Lee
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA (Reungsang, P.)
Abstract	The need for a low power, high performance embedded processor has grown at a very fast pace in recent years. Embedded processors require smaller cache size for low power system-on-a-chip consideration. Decreasing cache size leads to reduced power consumption because a smaller cache has less capacitance from the bit array size as well as smaller drivers in decoder or peripheral circuitry.. Unfortunately, performance also decreases due to a lower cache hit rate when the cache size becomes smaller. Recently, to improve the miss rate on a cache, many prefetching schemes have been introduced. However, on a small cache, prefetching schemes do not perform well because projected data replace the data that a processor will need in the future. This causes cache pollution, which degrades system performance. To overcome the cache pollution on a small cache, the paper introduces a new technique called "Fixed Prefetch Block" that integrates with the prefetching scheme. To evaluate the effectiveness of our scheme, extensive stimulations on SPEC95 integer benchmarks and Mediabench benchmarks suites were performed. Results from the simulations indicate that with our proposed technique, cache pollution can be reduced on a small set associative cache.
Sponsorship	IEEE Comput. Soc.
Starting Page	530
Ending Page	533
File Size	382178
Page Count	4
File Format	PDF
ISBN	0769512003
ISSN	10636404
DOI	10.1109/ICCD.2001.955085
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-09-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pollution Prefetching Power systems Energy consumption Capacitance Driver circuits Decoding Degradation System performance Performance evaluation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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