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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Fallah, F. Takayama, K. |
| Copyright Year | 2001 |
| Description | Author affiliation: Fujitsu Labs. of America Inc, Sunnyvale, CA, USA (Fallah, F.) |
| Abstract | This paper introduces a new method for manually generating test programs to validate a processor design. Current manual methods do not utilize high level of abstraction for describing test programs and lack many important features like reusability, incremental validation, and test program compaction; they also work on a formal model specifically developed for validation purposes. To solve the above problems, we use test specification expressions to describe test programs and generate test sequences based on an instruction-set description of a processor written for synthesis purposes. We provide experimental results of generating test programs for several processors to show the effectiveness of our method. |
| Sponsorship | IEEE Comput. Soc. |
| Starting Page | 76 |
| Ending Page | 81 |
| File Size | 645928 |
| Page Count | 6 |
| File Format | |
| ISBN | 0769512003 |
| ISSN | 10636404 |
| DOI | 10.1109/ICCD.2001.955006 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-09-23 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Process design Assembly Productivity Writing Manuals Compaction Automatic testing Test pattern generators Digital systems Design methodology |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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