NDLI: Selecting a well distributed hard case test suite for IEEE standard floating point division

Content Provider	IEEE Xplore Digital Library
Author	McFearin, L.D. Matula, D.W.
Copyright Year	2001
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA (McFearin, L.D.)
Abstract	We investigate two sets of hard to round p/spl times/p bit fractions arising from division of a normalized p bit floating point dividend by a normalized p bit floating point divisor. These sets can be characterized by the p/spl times/p bit fraction's quotient bit string, beginning with or just after the round bit, having the maximum number (p-1) of repeating like bits, specifically 00...01 or 11:..10 for the directed rounding "RD-hard" set and 100...01 or 011...10 for the round-to-nearest "RN-hard" set. We describe an algorithm for generating both the RD-hard and RN-hard sets in order of quotient value for any p, and use properties of fractions and continued fractions to characterize the distribution of these sets based on numerator, denominator, and quotient values. As a practical chip test example we summarize test runs showing our hard to round test suites are several orders of magnitude more efficient than random testing in finding erroneous quotients computed by the 1993 Pentium Processor having the well known fdiv flaw.
Sponsorship	IEEE Comput. Soc.
Starting Page	89
Ending Page	96
File Size	726464
Page Count	8
File Format	PDF
ISBN	0769512003
ISSN	10636404
DOI	10.1109/ICCD.2001.955008
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-09-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer aided software engineering Testing Iterative algorithms Arithmetic Computer science Character generation Hardware Algorithm design and analysis Table lookup Chip scale packaging
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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