NDLI: Architectural enhancements for fast subword permutations with repetitions in cryptographic applications

Content Provider	IEEE Xplore Digital Library
Author	McGregor, J.P. Lee, R.B.
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. Eng., Princeton Univ., NJ, USA (McGregor, J.P.)
Abstract	We propose two new instructions, swperm and sieve, that can be used to efficiently complete an arbitrary bit-level permutation of an n-bit word with or without repetitions. Permutations with repetitions are rearrangements of an ordered set in which elements may replace other elements in the set; such permutations are useful in cryptographic algorithms. On a 4-way superscalar processor, an arbitrary 64-bit permutation with repetitions of 1-bit subwords can be completed in 11 instructions and only 4 cycles using the two proposed instructions. For subwords of size 4 bits or greater, an arbitrary, permutation with repetitions of a 64-bit register can be completed in a single cycle using a single swperm instruction. This improves upon previous permutation instruction proposals that require log(r) sequential instructions to permute r subwords of a 64-bit word without repetitions. Our method requires fewer instructions to permute 4-bit or larger subwords packed in a 64-bit register and fewer execution cycles for 1-bit subwords on wide superscalar processors.
Sponsorship	IEEE Comput. Soc.
Starting Page	453
Ending Page	461
File Size	870356
Page Count	9
File Format	PDF
ISBN	0769512003
ISSN	10636404
DOI	10.1109/ICCD.2001.955065
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-09-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cryptography Table lookup Registers Arithmetic Software performance Cellular neural networks Proposals Data security Microprocessors Sun
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Architectural techniques for accelerating subword permutations with repetitions

Fast subword permutation instructions using omega and flip network stages

Bit permutation instructions for accelerating software cryptography

The analysis of a new class of unbalanced CAST ciphers

Architectural enhancements for fast subword permutations with repetitions in cryptographic applications (2001).

From Cryptography to Hardware: Analyzing Embedded Xilinx BRAM for Cryptographic Applications

Processor accelerator for AES

Subword Permutations with MIX Instructions

Efficient Residue Reduction Algorithm using DSP Circular Buffer Registers

Architectural enhancements for fast subword permutations with repetitions in cryptographic applications

Similar Documents

Architectural techniques for accelerating subword permutations with repetitions

Fast subword permutation instructions using omega and flip network stages

Bit permutation instructions for accelerating software cryptography

The analysis of a new class of unbalanced CAST ciphers

Architectural enhancements for fast subword permutations with repetitions in cryptographic applications (2001).

From Cryptography to Hardware: Analyzing Embedded Xilinx BRAM for Cryptographic Applications

Processor accelerator for AES

Subword Permutations with MIX Instructions

Efficient Residue Reduction Algorithm using DSP Circular Buffer Registers

Architectural enhancements for fast subword permutations with repetitions in cryptographic applications