NDLI: Power efficient data cache designs

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Energy efficient asymmetrically ported register files

Power efficient data cache designs

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Power efficient data cache designs

Content Provider	IEEE Xplore Digital Library
Author	Abella, J. Gonzalez, A.
Copyright Year	2003
Description	Author affiliation: Comput. Archit. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain (Abella, J.; Gonzalez, A.)
Abstract	We investigate some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in performance. The basic idea is to combine different threshold voltages with different cache organizations that provide different levels of performance. Multibanked organizations in combination with different approaches to allocate data to cache banks are explored. Some of the resulting cache architectures are shown to provide a good tradeoff between power and performance.
Sponsorship	IEEE Comput. Soc. IEEE Circuits & Syst. Soc. IEEE Electron Devices Soc
Starting Page	8
Ending Page	13
File Size	274045
Page Count	6
File Format	PDF
ISBN	0769520251
ISSN	10636404
DOI	10.1109/ICCD.2003.1240866
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-10-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power dissipation Threshold voltage Circuits Energy consumption Process design Low voltage Power system modeling Capacitance Computer architecture Signal processing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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