NDLI: An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving

Content Provider	IEEE Xplore Digital Library
Author	Anh Tuan Do Kiat Seng Yeo Low, J.Y.S. Low, J.Y.L. Zhi Hui Kong
Copyright Year	2010
Description	Author affiliation: Centre for Integrated Circuits and Systems (CICS), School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore (Anh Tuan Do; Kiat Seng Yeo; Low, J.Y.S.; Low, J.Y.L.; Zhi Hui Kong)
Abstract	Lowering power consumption and increasing noise margin have become two central topics in every state of the art SRAM design. Several 8T and 10T cell designs have been reported, improving the cell stability of the conventional 6T. In this paper, we use a fully differential 8T SRAM that removes the half-accessed issue to allow an efficient bit-interleaving implementation. It also consumes less power when compared to the conventional 6T design. A column-based dynamic supply voltage scheme is utilized to improve both the read noise margin and the write-ability. A 128×64-bit of the proposed SRAM has been implemented in a standard 65 nm/ 1V CMOS process. Simulation results reaffirmed that the proposed design has 2x higher noise margin and consumes 46% less power when compared to the conventional 6T design at 1 V supply voltage.
Starting Page	704
Ending Page	707
File Size	539296
Page Count	4
File Format	PDF
ISBN	9781424474547
e-ISBN	9781424474561
DOI	10.1109/APCCAS.2010.5774810
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-06
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Microprocessors Random access memory Transistors Noise Circuit stability Stability analysis WTP SRAM bit-interleaving half-accessed SNM
Content Type	Text
Resource Type	Article

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