NDLI: A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators

Content Provider	IEEE Xplore Digital Library
Author	Yang Jiang Kim-Fai Wong Chen-Yan Cai Sai-Weng Sin Seng-Pan U. Martins, R.P.
Copyright Year	2010
Description	Author affiliation: Analog and Mixed Signal VLSI Laboratory, Faculty of Science and Technology, University of Macau, Macao, China (Yang Jiang; Kim-Fai Wong; Chen-Yan Cai; Sai-Weng Sin; Seng-Pan U; Martins, R.P.)
Abstract	A clock generation technique for reducing the clock-jitter sensitivity of Switched current (SI) Return-to-Zero (RZ) DAC in CT ΣΔ modulators is presented in this paper. While realizing the clock-jitter insensitivity, this technique ensures that the feedback period can be utilized more efficiently so that the amplitude of feedback current can be reduced. The proposed technique employs simple digital elements to generate a fixed-pulse-width feedback control clock. It was verified in a $2^{nd}$ order, 1-bit CT ΣΔ modulator with SI RZ feedback. Simulation result shows that the clock-jitter tolerance using the proposed technique is up to 2% of a clock cycle with SNDR larger than 62dB. While using the traditional clock generation method, clock-jitter tolerance is only 0.1% of a clock cycle.
Starting Page	1011
Ending Page	1014
File Size	1240275
Page Count	4
File Format	PDF
ISBN	9781424474547
e-ISBN	9781424474561
DOI	10.1109/APCCAS.2010.5774943
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-06
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Jitter Silicon Noise Shape Modulation Sensitivity switched current DAC Clock-jitter sensitivity continuous-Time sigma-delta modulator
Content Type	Text
Resource Type	Article

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