NDLI: Impact of HALO structure on threshold voltage and leakage current in 45nm NMOS device

Content Provider	IEEE Xplore Digital Library
Author	Salehuddin, F. Ahmad, I. Hamid, F.A. Zaharim, A.
Copyright Year	2010
Description	Author affiliation: Faculty of Engineering and Built Environment, Universiti Kebangsaan Malaysia (UKM), Bangi, Selangor, Malaysia (Zaharim, A.) \|\| College of Engineering, Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor, Malaysia (Salehuddin, F.; Ahmad, I.; Hamid, F.A.)
Abstract	In this paper, we investigate the impact of process parameter like halo structure on threshold voltage (VTH) and leakage current (ILeak) in 45nm NMOS device. The settings of process parameters were determined by using Taguchi experimental design method. Besides halo implant, the other process parameters which used were Source/Drain (S/D) implant and oxide growth temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to threshold voltage and leakage current are oxide growth temperature (71%) and S/D implant dose (47%) respectively. Whereas the second ranking factor affecting VTH and ILeak are halo implant tilt (15%) and halo implant dose (35%) respectively. As conclusions, S/D implant dose and oxide growth temperature have the strongest effect on the response characteristics. The results show that the VTH for NMOS device equal to 0.150V at tox= 1.1nm. The results show that ILeak after optimizations approaches is 51.8µA/µm.
Starting Page	1147
Ending Page	1150
File Size	469148
Page Count	4
File Format	PDF
ISBN	9781424474547
e-ISBN	9781424474561
DOI	10.1109/APCCAS.2010.5774934
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-06
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Implants MOS devices Threshold voltage Leakage current Optimization Transistors Analysis of variance Taguchi Method NMOS Device Threshold Voltage Leakage Current
Content Type	Text
Resource Type	Article

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