NDLI: An efficient architecture of DCTQ module in MPEG-4 video codec

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On power allocation for generalized cyclic-prefix based channel-equalizers

An improved peak-to-average-power ratio reduction algorithm for multicarrier communications

Subspace estimation-based constrained optimization method for multipath CDMA channels

Enhancing robustness of information hiding against interference of communication with turbo code

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A generalized methodology for lower-error area-efficient fixed-width multipliers

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Maximum achievable energy reduction using coding with applications to deep sub-micron buses

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Post-compensation of RF non-linearity in mobile OFDM systems by estimation of memory-less polynomial

Accurate CMOS implementation of PWL CNN neuron activations

Initiation and tracking of dim target via fusion of feature probabilities with CNN-UM

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Further results on blind equalization and estimation of SIMO time-varying channels

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MIMO wireless channels made simple

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Fast soft-output Viterbi decoding for duo-binary turbo codes

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Dynamic stage matching for parallel pipeline A/D converters

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A pipelined A/D converter for high-speed and high-resolution application

Design of low-voltage CMOS pipelined ADCs using 1 pico-Joule of energy per conversion

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An efficient architecture of DCTQ module in MPEG-4 video codec

Content Provider	IEEE Xplore Digital Library
Author	Kibum suh Seongmo Park Seongmin Kim Bontae Koo Igkyun Kim Kyungsoo Kim Hanjin Cho
Copyright Year	2002
Description	Author affiliation: Electron. Eng. Dept., Woosong Univ., Taejeon, South Korea (Kibum suh)
Abstract	In this paper, a VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the DCTQ is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling CIF image formats. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27 MHz clock. The area is 50 % smaller than the previous methods with 2D-DCT and IDCT. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.
Sponsorship	IEEE IEEE Circuits & Syst. Soc
File Size	300432
File Format	PDF
ISBN	0780374487
DOI	10.1109/ISCAS.2002.1009956
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MPEG 4 Standard Video codecs Discrete cosine transforms Quantization Hardware Very large scale integration Image converters Arithmetic Energy consumption Clocks
Content Type	Text
Resource Type	Article

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