NDLI: A new group distributed arithmetic design for the one dimensional discrete Fourier transform

Please wait, while we are loading the content...

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

2012 IEEE International Conference on Circuits and Systems (ICCAS)

2012 IEEE International Symposium on Circuits and Systems

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

2009 IEEE International Symposium on Circuits and Systems

2008 IEEE International Symposium on Circuits and Systems

2007 IEEE International Symposium on Circuits and Systems

2006 IEEE International Symposium on Circuits and Systems

2005 IEEE International Symposium on Circuits and Systems

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003.

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

Volume 5 - 2002

Volume 4 - 2002

Volume 3 - 2002

Volume 2 - 2002

Volume 1 - 2002

On power allocation for generalized cyclic-prefix based channel-equalizers

An improved peak-to-average-power ratio reduction algorithm for multicarrier communications

Subspace estimation-based constrained optimization method for multipath CDMA channels

Enhancing robustness of information hiding against interference of communication with turbo code

Successive packing based interleaver design for turbo codes

A parallel fast algorithm of Volterra adaptive filters

An improved stochastic model for the least mean fourth (LMF) adaptive algorithm

A piecewise linear dynamical functional artificial neural network (PWL-DFANN) for nonlinear adaptive time series prediction

Learning characteristics of adaptive fault tolerant filters in the presence of transient errors

Pipelined RLS adaptive architecture using relaxed Givens rotations (RGR)

Third-generation and beyond (3.5G) wireless networks and its applications

Adaptive playout for real-time media streaming

Robust video multicast under rate and channel variability with applications to wireless LANs

Adaptive end-to-end optimization of mobile video streaming using QoS negotiation

Video transport over ad-hoc networks using multiple paths

Error robust video transmission over wireless IP networks with multiuser detection

A generalized methodology for lower-error area-efficient fixed-width multipliers

Design of low error CSD fixed-width multiplier

Extended results for minimum-adder constant integer multipliers

The use of reduced two's-complement representation in low-power DSP design

A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers

Maximum achievable energy reduction using coding with applications to deep sub-micron buses

A novel analysis method of bus signal transmission and a proposal for high-speed low-power bus circuit

Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding

On dynamic delay and repeater insertion

Inductance/area/resistance tradeoffs in high performance power distribution grids

A necessary and sufficient condition for mismatch shaping in multi-bit DACs

Design of oversampling current steering DAC with 640 MHz equivalent clock frequency

A differential DAC architecture with variable common-mode level

A general analysis on the timing jitter in D/A converters

A 14-bit, 40-MS/s DAC with current mode deglitcher

A very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applications

Charge sampling mixer with /spl Delta//spl Sigma/ quantized impulse response

Low noise, high linearity double-balanced active mixers using lossless feedback

GHz programmable dual-modulus prescaler for multi-standard wireless applications

A direct digital RF amplitude modulator

A substrate noise circuit for accurately testing mixed-signal ICs

Built-in self-test scheme for on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard

A neural network approach for fault diagnosis of large-scale analogue circuits

The qualitative form of optimum transient test signals for analog circuits derived from control theory methods

Fault location of single-phase transmission lines by Laguerre function

A novel and efficient timing-driven global router for standard cell layout design based on critical network concept

On segmented channel routability

Gated direct sequence spread spectrum clocking scheme for multimedia systems

Wavelet method for high-speed clock tree simulation

Design flow of robust routed power distribution for low power ASIC

Space-time blind adaptive multiuser detection in antenna array CDMA systems

Suppression of bit-pulsed jammer signals in DS-CDMA array system using independent component analysis

Multiuser wavelet based MC-CDMA receiver with linearly constrained constant modulus IQRD-RLS algorithm

State space blind source recovery for mixtures of multiple source distributions

Wavelet denoising for highly noisy source separation

Adaptive antenna systems for mobile ad-hoc networks

Channel identification scheme for modified MC-CDMA systems with the mixing model of replicating and serial-to-parallel converting

Subspace-based estimation method of uplink FIR channel in MC-CDMA system without cyclic prefix over frequency-selective fading channel

Post-compensation of RF non-linearity in mobile OFDM systems by estimation of memory-less polynomial

Accurate CMOS implementation of PWL CNN neuron activations

Initiation and tracking of dim target via fusion of feature probabilities with CNN-UM

On the existence of stable equilibrium points in cellular neural networks

Progressive image reconstruction via cellular neural networks

The template optimization of discrete time CNN for image compression and reconstruction

Analysis of time-controlled switched systems using stability preserving mappings

Criteria for asymptotic stability of a class of discrete systems with multiple independent variables

Stabilizing linear time-invariant systems with finite-state hybrid static output feedback

Stability and linearization: discrete-time systems

The Cauchy-Floquet factorization by successive Riccati transformations

A trace-back-free Viterbi decoder using a new survival path management algorithm

Power reduction techniques for an OFDM burst synchronization core

Parasitic-aware synthesis of RF CMOS switching power amplifiers

Minimum power broadcast trees for wireless networks: optimizing using the viability lemma

Low power SOVA architecture using bi-directional scheme

Interpolation of discrete periodic nonuniform decimation using alias unraveling

Low coefficient complexity approximations of the one dimensional discrete cosine transform

Error spectrum shaping in closed-loop systems with state-estimate feedback controller

Design of a DSP-based 24 bit digital audio equalizer for automotive applications

Power analysis of multiplier blocks

A high-bandwidth high-swing CMOS power amplifier for portable audio players

Comparison of two schemes for continuous-time sub-volt op-amp operation

An 1 V rail-rail low-power CMOS op-amp

Inverting the bipolar differential pair for low-voltage applications

1.8 V low voltage pseudo-differential input operational amplifier

Analysis and optimization of gain-boosted telescopic amplifiers

Low-voltage, low-power and high gain CMOS operational transconductance amplifier

Rail-to-rail OTA using a pair of single channel type MOSFETs

A reliable 5V OTA in 3.3V CMOS technology

A 1.2 V rail-to-rail differential mode input linear CMOS transconductor

Sequence-pair based placement with boundary constraints

A genetic approach to analog module placement with simulated annealing

Module placement with pre-placed modules using the corner block list representation

An effective floorplan-based power distribution network design methodology under reliability constraints

Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits

Optimal adaptive bandwidth monitoring for QoS based retrieval

Joint source-channel content-based multistream video coding scheme

TDMA-based communication scheduling in system-on-chip video encoder

Recursive patching for video-on-demand (VOD) systems with limited client buffer constraint

Dynamic throughput estimation for wireless multimedia transmission

Analysis of the oscillation problem in tri-flops

Experimental detection of bifurcations and sliding in DC-DC power converters

An advanced design method of bursting in Fitzhugh-Nagumo model

Performance analysis in chaotic-iteration-based ADCs

An optimal estimation algorithm for multiuser chaotic communications systems

Optimal design and parallel implementation of FIR filters with variable magnitude and fractional-delay responses

A design method of low delay lowpass FIR filters with maximally flat characteristics in the passband and the transmission zeros in the stopband

Minimax design of nonlinear-phase FIR filters: a least-pth approach

On designing FIR filters using windows based on Gegenbauer polynomials

Intelligent multipoint Arnoldi (IMA) approximations of FIR filters by low-order linear-phase IIR filters

A new group distributed arithmetic design for the one dimensional discrete Fourier transform

A retargetable tool-suite for the design of application specific instruction set processors using a machine description language

Comparison of digital linearization methods for embedded sensor interfaces

ASIC implementation architecture for pulse shaping FIR filters in 3G mobile communications

Real-time streaming for the animation of talking faces in multiuser environments

Layered video over IP networks by using selective drop routers

FGS+: optimizing the joint SNR-temporal video quality in MPEG-4 fine grained scalable coding

Video coding with virtual set partitioning in hierarchical tree

TCP-compatible rate control for FGS layered multicast video transmission based on a clustering algorithm

A 3.3 V 1 GHz high speed pipelined Booth multiplier

A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme

An interconnect optimized floorplanning of a scalar product macrocell

Low depth carry lookahead addition using charge recycling threshold logic

A robust self-resetting CMOS 32-bit parallel adder

Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization

Architectural approaches to reduce leakage energy in caches

Optimizing finite state machines for system-on-chip communication

Two-dimensional signal gating for low-power array multiplier design

Low-power methodology issues in digital circuit design

A 15-bit CMOS cyclic A/D converter with correlated double sampling

A 10-bit 1 MS/s 3-step ADC with bitstream-based sub-DAC and sub-ADC calibration

An analog-to-digital converter with time-variant window

Wallace tree encoding in folding and interpolation ADCs

A nonlinearity-corrected CMOS time digitizer IC with 20 ps single-shot precision

Single-amplifier integrator-based low power CMOS filter for video frequency applications

A loss control feedback loop for VCO stable amplitude tuning of RF integrated filters

Complex low-pass filters

Properties of RF bandpass amplifier topology with Q-enhancing

WCDMA channel selection filter with high IIP2

A limitation on active filter dynamic range

Nomographs and classical filter sensitivity optimization

Continuous-time linear systems: folklore and fact

Statistical analysis of switched linear networks

A maximum power transfer theorem for DC linear two-ports

Floating-gate EEPROM cell: threshold voltage sensibility to geometry

Analysis of power supply noise attenuation in a PTAT current source

Tolerance analysis for electronic circuit design using the method of moments

Modeling hot-electrons effects in silicon-on-sapphire MOSFETs

A neural network approach to predict the crosstalk in non-uniform multiconductor transmission lines

A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL

Automated test development and test time reduction for RF subsystems

A heuristic DSP BIST insertion algorithm with minimum area overhead

Practical solutions for the application of the oscillation-based-test in analog integrated circuits

Low-voltage analog current detector supporting at-speed BIST

Monocycle shapes for ultra wideband system

Joint space-multipath-Doppler RAKE receiving in DS-CDMA systems over time-selective fading channels

Error correction block based ARQ protocol for wireless digital video transmission

Iteration reduction of turbo decoders using an efficient stopping/cancellation technique

Performance of active codes detection algorithms for the downlink of TD-SCDMA system

A search algorithm for the design of multinested cellular neural networks

Cell and network level design of a mixed-mode CNN

On the optimal choice of integration time-step for raster simulation of a CNN for gray level image processing

Improvement of pattern learning and recognition capability in ratio-memory cellular neural networks with non-discrete-type Hebbian learning algorithm

Necessary and sufficient conditions for one-dimensional discrete-time binary cellular neural networks with both A- and B-templates to be stable

Harmonic balance and almost periodic inputs

Frequency response of nonlinear networks using curve tracing algorithm

HomSSPICE: a homotopy-based circuit simulator for periodic steady-state analysis of oscillators

Tolerance analysis of nonlinear circuits using set-valued functions

Hardware implementation of Moore test on FPGA

A MEMS socket system for high density SoC interconnection

Ultrasonic bearing estimation using a MEMS microphone array and spatiotemporal filters

Design, double sided post-processing, and packaging of CMOS compatible bio-MEMS device arrays

Improved data acquisition system for digital flow cytometry

Logarithmic programmable preamplifier dedicated to ultrasonic receivers

A multirate approach to multichannel blind deconvolution

A new blind signature waveform estimation approach in antenna array CDMA systems

Blind electromagnetic source separation and localization

Reduced-dimension multiuser detection based on grouping users and reducing effective length of spread spectrum code in CDMA systems

On the design of digital broadband beamformer for uniform circular array with frequency invariant characteristics

Blind space-time multiuser detector

All digital transistor high gain operational amplifier using positive feedback technique

Novel high performance current-feedback op-amp

A CMOS current feedback operational amplifier with active current mode compensation

A temperature independent trimmable current source

Temperature compensated CMOS voltage reference

Determination of voltage source values in modern biasing techniques of analog circuits

A low-noise nonlinear feedback technique for compensating offset in analog multipliers

A new wideband BiCMOS four-quadrant analog multiplier

Modified Gilbert transconductance multiplier

Useful multipliers for low-voltage applications

A CAD-oriented method for optimal biasing of amplifiers

GENOM: circuit-level optimizer based on a modified genetic algorithm kernel

Synthesis and optimization of analog VLSI filters from VHDL-AMS parse trees

An interval arithmetic-based yield evaluation in circuit tolerance design

A new approach to modeling statistical variations in MOS transistors

Multiple sequence families with efficient hardware architecture for use in spread spectrum watermarking

A high performance JPEG2000 architecture

Optimization of portable system architecture for real-time 3D graphics

Efficient pass-parallel architecture for EBCOT in JPEG2000

An efficient architecture of DCTQ module in MPEG-4 video codec

Lossless, near-lossless and lossy adaptive coding based on the lossless DCT

Canny edge based image expansion

Lossless wavelet image coding using layered coefficient partitioning

Vector quantization fast search algorithm using hyperplane based k-dimensional multi-node search tree

A hierarchical fast encoding algorithm for vector quantization with PSNR equivalent to full search

Design of two-dimensional cosine-modulated oversampled FIR filter banks: PR condition

Nonlinear processing of n-dimensional phase signals

Non-uniform bandwidth frequency-planar (NUB-FP) filter banks

New design methods of FIR filters with signed power of two coefficients based on a new linear programming relaxation with triangle inequalities

Results on a class of biorthogonal 2-D LP FIR filter banks

Design of prototype filter for near-perfect-reconstruction overlapped complex-modulated transmultiplexers

An efficient approach for designing nearly perfect-reconstruction low-delay cosine-modulated filter banks

Step-response-based characterization of nonuniform perfect-reconstruction filter banks

Complex modulated critically sampled filter banks based on cosine and sine modulation

Application of unimodular matrices to signal compression

Chip-interleaved block-spread CDMA for the downlink with inter-cell interference and soft hand-off

Blind equalization by sequential importance sampling

A new algorithm for QAM signal classification in AWGN channels

Further results on blind equalization and estimation of SIMO time-varying channels

Space-time codes for high bit rate wireless communications: asymptotic performance of space-time random codes

MIMO wireless channels made simple

Low-voltage micropower asynchronous multiplier for hearing instruments

Low cost floating-point unit design for audio applications

Low-voltage asynchronous adders for low power and high speed applications

A novel floating-gate multiple-valued CMOS full-adder

Multi-valued logic function implementation with novel current-mode logic gates

Fast soft-output Viterbi decoding for duo-binary turbo codes

High-speed add-compare-select units using locally self-resetting CMOS

A reconfigurable superimposed 2D-mesh array for channel equalization

Enabling high-speed turbo-decoding through concurrent interleaving

High speed VLSI architecture design for block turbo decoder

Dynamic stage matching for parallel pipeline A/D converters

High-speed pipelined A/D converter using time-shifted CDS technique

A 115mW 12-bit 50 MSPS pipelined ADC

A pipelined A/D converter for high-speed and high-resolution application

Design of low-voltage CMOS pipelined ADCs using 1 pico-Joule of energy per conversion

Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)

Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97

1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

1993 IEEE International Symposium on Circuits and Systems

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems

1991., IEEE International Sympoisum on Circuits and Systems

IEEE International Symposium on Circuits and Systems

IEEE International Symposium on Circuits and Systems,

1988., IEEE International Symposium on Circuits and Systems

A new group distributed arithmetic design for the one dimensional discrete Fourier transform

Content Provider	IEEE Xplore Digital Library
Author	Hun-Chen Chen Jiun-In Guo Chien-Wei Jen
Copyright Year	2002
Description	Author affiliation: Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan (Hun-Chen Chen)
Abstract	This paper presents a new group distributed arithmetic (GDA) design for the one-dimensional discrete Fourier transform (1-D DFT). We adopt distributed arithmetic (DA) computation and exploit the good features of the cyclic convolution to facilitate an efficient realization of one-dimensional N-point DFT using ROM module with small size, a barrier shifter, and N accumulators. To increase the ROM utilization, we re-arrange the content of ROM into several groups in which all the elements in a group will be accessed simultaneously in accumulating all the DFT outputs in word-parallel and bit-serial manner. It is called the GDA design approach in this paper. To compare the results with the traditional DA design, the design with the proposed approach can reduce significantly both the hardware cost and the propagation delay.
Sponsorship	IEEE IEEE Circuits & Syst. Soc
File Size	392377
File Format	PDF
ISBN	0780374487
DOI	10.1109/ISCAS.2002.1009867
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Arithmetic Discrete Fourier transforms Read only memory Convolution Hardware Costs Signal processing algorithms Design engineering Very large scale integration Systolic arrays
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in