NDLI: A CAD-oriented method for optimal biasing of amplifiers

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On power allocation for generalized cyclic-prefix based channel-equalizers

An improved peak-to-average-power ratio reduction algorithm for multicarrier communications

Subspace estimation-based constrained optimization method for multipath CDMA channels

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A generalized methodology for lower-error area-efficient fixed-width multipliers

Design of low error CSD fixed-width multiplier

Extended results for minimum-adder constant integer multipliers

The use of reduced two's-complement representation in low-power DSP design

A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers

Maximum achievable energy reduction using coding with applications to deep sub-micron buses

A novel analysis method of bus signal transmission and a proposal for high-speed low-power bus circuit

Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding

On dynamic delay and repeater insertion

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A necessary and sufficient condition for mismatch shaping in multi-bit DACs

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A differential DAC architecture with variable common-mode level

A general analysis on the timing jitter in D/A converters

A 14-bit, 40-MS/s DAC with current mode deglitcher

A very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applications

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A direct digital RF amplitude modulator

A substrate noise circuit for accurately testing mixed-signal ICs

Built-in self-test scheme for on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard

A neural network approach for fault diagnosis of large-scale analogue circuits

The qualitative form of optimum transient test signals for analog circuits derived from control theory methods

Fault location of single-phase transmission lines by Laguerre function

A novel and efficient timing-driven global router for standard cell layout design based on critical network concept

On segmented channel routability

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Wavelet method for high-speed clock tree simulation

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Space-time blind adaptive multiuser detection in antenna array CDMA systems

Suppression of bit-pulsed jammer signals in DS-CDMA array system using independent component analysis

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Post-compensation of RF non-linearity in mobile OFDM systems by estimation of memory-less polynomial

Accurate CMOS implementation of PWL CNN neuron activations

Initiation and tracking of dim target via fusion of feature probabilities with CNN-UM

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Progressive image reconstruction via cellular neural networks

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Stability and linearization: discrete-time systems

The Cauchy-Floquet factorization by successive Riccati transformations

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Further results on blind equalization and estimation of SIMO time-varying channels

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MIMO wireless channels made simple

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Low cost floating-point unit design for audio applications

Low-voltage asynchronous adders for low power and high speed applications

A novel floating-gate multiple-valued CMOS full-adder

Multi-valued logic function implementation with novel current-mode logic gates

Fast soft-output Viterbi decoding for duo-binary turbo codes

High-speed add-compare-select units using locally self-resetting CMOS

A reconfigurable superimposed 2D-mesh array for channel equalization

Enabling high-speed turbo-decoding through concurrent interleaving

High speed VLSI architecture design for block turbo decoder

Dynamic stage matching for parallel pipeline A/D converters

High-speed pipelined A/D converter using time-shifted CDS technique

A 115mW 12-bit 50 MSPS pipelined ADC

A pipelined A/D converter for high-speed and high-resolution application

Design of low-voltage CMOS pipelined ADCs using 1 pico-Joule of energy per conversion

Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)

Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97

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A CAD-oriented method for optimal biasing of amplifiers

Content Provider	IEEE Xplore Digital Library
Author	Sarmiento-Reyes, L.A. Yildiz, E. Verhoeven, C.J.M. van Staveren, A.
Copyright Year	2002
Description	Author affiliation: Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands (Sarmiento-Reyes, L.A.; Yildiz, E.; Verhoeven, C.J.M.; van Staveren, A.)
Abstract	In the automated design of amplifier circuits, the biasing constitutes a serious obstacle that is usually overcome by resorting to the application of heuristics or thumb rules based on the experience of the designer. In fact, biasing can be regarded as the procedure that results in smartly placed bias sources of the amplifier while keeping its small-signal behaviour intact. This paper introduces a CAD methodology that uses the circuit topology on its full extent in combination with some design-driven criteria in order to determine the optimal placement of the bias sources. The method is based on the concepts of current-stimuli and voltage-stimuli graphs. A dynamic deformation of the trees and co-trees of both graphs is achieved with the aim of obtaining the appropriate placement of the bias sources.
Sponsorship	IEEE IEEE Circuits & Syst. Soc
File Size	290545
File Format	PDF
ISBN	0780374487
DOI	10.1109/ISCAS.2002.1009947
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Tree graphs Circuit topology Integrated circuit modeling Laboratories Sorting Thumb Design automation Design optimization Bandwidth
Content Type	Text
Resource Type	Article

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