NDLI: Optimization of portable system architecture for real-time 3D graphics

Content Provider	IEEE Xplore Digital Library
Author	Ju-ho Sohn Woo, Ramchan Hoi-Jun Yoo
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejon, South Korea (Ju-ho Sohn; Ramchan Woo; Hoi-Jun Yoo)
Abstract	The optimal architecture of personal digital assistants (PDA) system for real-time 3D graphics was analyzed by simulating the 3D applications on the various Advanced RISC Machines (ARM) processor platforms. Simulation results show that for 256/spl times/256 screen resolution, even the performance of 200 MHz StrongARM with 160 MHz floating point unit (FPU) shows only 1.78 % of the requirement of full 3D pipeline. To realize the real-time 3D graphics on PDA, the optimal architecture must contain hardware acceleration engine with embedded DRAM as the rendering stage. In this architecture, MAC-enhanced ARM9 without FPU that is used as a host processor can provide the necessary geometry operations and we verified this architecture by the implementation of a PDA chip.
Sponsorship	IEEE IEEE Circuits & Syst. Soc
File Size	470627
File Format	PDF
ISBN	0780374487
DOI	10.1109/ISCAS.2002.1009954
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Real time systems Graphics Personal digital assistants Analytical models Reduced instruction set computing Pipelines Hardware Acceleration Engines Random access memory
Content Type	Text
Resource Type	Article

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