NDLI: Built-in self-test scheme for on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard

Content Provider	IEEE Xplore Digital Library
Author	Acevedo, G.O.D. Ramirez-Angulo, J.
Copyright Year	2002
Description	Author affiliation: Klipsch Sch. of Electr. & Comput. Eng., New Mexico State Univ., Las Cruces, NM, USA (Acevedo, G.O.D.; Ramirez-Angulo, J.)
Abstract	This paper presents a testing scheme for analog and mixed-signal circuitry compatible with the IEEE 1149.4 mixed-signal test bus standard. An innovative self-diagnostic method called VDDQ is proposed. The proposed method performs a pass or fail function which sequentially senses quiescent voltage on several nodes of the circuit under test and compares them with their nominal value. The output is a digital flag that passes or fails the nodes accessed. Simulation results are provided for the flag and amplifier circuit used for the design of the testing circuit. Through simulations this test has performed testing one node every millisecond. This testing scheme is at least 12 times faster than currently used methods in industry, which average to 5000 nodes per minute. This will potentially allow a defect free IC to enter the market in significantly less time than with conventional testing methods.
Sponsorship	IEEE IEEE Circuits & Syst. Soc
File Size	390350
File Format	PDF
ISBN	0780374487
DOI	10.1109/ISCAS.2002.1009799
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Automatic testing Circuit testing Voltage Circuit faults Performance evaluation Circuit simulation Analog circuits Manufacturing Analog computers
Content Type	Text
Resource Type	Article

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