NDLI: Design of oversampling current steering DAC with 640 MHz equivalent clock frequency

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Design of oversampling current steering DAC with 640 MHz equivalent clock frequency

Content Provider	IEEE Xplore Digital Library
Author	Yunyoung Choi Maloberti, F.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA (Yunyoung Choi)
Abstract	Recent mobile communications demand high-speed and high-resolution data converters for digital signal processing (DSP) in the receiver and transceiver of the communication systems. Those applications require more than 14-bit resolution and several hundred of MHz bandwidth. In this paper, we propose a new sigma-delta parallel DAC (Digital-to-Analog Converter) structure that achieves the required accuracy with 640 MHz clock frequency. The circuit employs current steering and multi-bit solution with matching technique. The entire architecture has been verified by simulations with a 0.18 /spl mu/m CMOS process (TI).
Sponsorship	IEEE IEEE Circuits & Syst. Soc
File Size	324829
File Format	PDF
ISBN	0780374487
DOI	10.1109/ISCAS.2002.1009789
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Digital signal processing Mobile communication Transceivers Signal resolution Bandwidth Delta-sigma modulation Digital-analog conversion Frequency conversion Circuits
Content Type	Text
Resource Type	Article

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