NDLI: A bit-serial column parallel processing architecture for on-sensor discrete Fourier transform

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New current-mode sense amplifiers for high density DRAM and PIM architectures

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A bit-serial column parallel processing architecture for on-sensor discrete Fourier transform

Content Provider	IEEE Xplore Digital Library
Author	Kawahitio, S. Eki, T. Tadokoro, Y.
Copyright Year	2001
Description	Author affiliation: Res. Inst. of Electron., Shizuoka Univ., Hamamatsu, Japan (Kawahitio, S.)
Abstract	Recent advances in CMOS image sensor technology allow us to realize highly-integrated imaging devices. This paper proposes an architecture of discrete Fourier transform (DFT) for integration on the CMOS image sensor. The proposed bit-serial column parallel DFT scheme is suitable for the integrated image sensor from the viewpoints of high-speed processing, cost-effective implementation, and matching with the column parallel A/D conversion architecture of the CMOS imager. In the case of 256/spl times/256-point DFT, the processing time is estimated to be 2 ms at clock frequency of 100 MHz, which corresponds to the 500 frame/s real-time processing.
Sponsorship	IEEE Circuits & Syst. Soc
Starting Page	738
Ending Page	741
File Size	359231
Page Count	4
File Format	PDF
ISBN	0780366859
DOI	10.1109/ISCAS.2001.922343
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-06
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel processing Discrete Fourier transforms CMOS image sensors Discrete cosine transforms Image converters Frequency estimation Real time systems Signal processing Circuits Image processing
Content Type	Text
Resource Type	Article

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