NDLI: Fast and low-power inner product processor

Content Provider	IEEE Xplore Digital Library
Author	Kazakova, N. Sung, R. Durdle, N. Margala, M. Lamoureux, J.
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada (Kazakova, N.)
Abstract	This paper describes a novel fast and low-power two's complement fixed-point inner product processor targeted for 3D volume rendering applications. The design was simulated and fabricated in a 0.18 /spl mu/m, six-metal, single-poly CMOS process. Speed and power optimizations were achieved at both the architecture and circuit levels. The inner product operation, consisting of multiplications and additions, is merged into a composite function in order to minimize circuit area, improve speed and minimize power dissipation. Individual functional blocks including the partial product: encoder, reduction tree and final two operand adder were built entirely using complementary pass transistor logic (CPL) with reduced swing internal nodes to minimize the energy required during switching. Simulated results for a (8/spl times/8/spl times/8)-b implementation showed an average evaluation time of 2.6 ns at 1.8 V. The average power dissipation at 200 MHz was 2.53 mW.
Sponsorship	IEEE Circuits & Syst. Soc
Starting Page	646
Ending Page	649
File Size	399543
Page Count	4
File Format	PDF
ISBN	0780366859
DOI	10.1109/ISCAS.2001.922320
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-06
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Computational modeling Circuit simulation Adders Power engineering computing Power dissipation Rendering (computer graphics) Biomedical imaging Data visualization Power system reliability
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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