NDLI: Leakage power estimation and minimization in VLSI circuits

Content Provider	IEEE Xplore Digital Library
Author	Wen-Tsong Shiue
Copyright Year	2001
Description	Author affiliation: Silicon Metrics Corp., Austin, TX, USA (Wen-Tsong Shiue)
Abstract	In low-power design for circuits, people want to reduce the power supply voltage, and this requires the transistor threshold voltages to also be reduced to maintain throughput and noise margins. However. This increases the subthreshold leakage current in p and n MOSFETs, which begins to increase the overall power in large circuits. Because the leakage power in CMOS gates has state dependent status, we solve this problem by choosing one specific state (the best state) with minimum leakage power in all input combinations. This implies that we can apply the best state for this CMOS gate when it is not activated (in idle mode). This helps to reduce leakage power dissipation in a large system. This paper shows how a linear programming model and a heuristic algorithm can be used to obtain we optimal solution in determining the best state with minimum leakage energy for CMOS gates such as Inverter, AND, OR, NAND, and NOR gates. The accurate close form model that is modified and used for estimation of the leakage power for CMOS gate.
Sponsorship	IEEE Circuits & Syst. Soc
Starting Page	178
Ending Page	181
File Size	393135
Page Count	4
File Format	PDF
ISBN	0780366859
DOI	10.1109/ISCAS.2001.922201
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-06
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Minimization Very large scale integration Circuits Threshold voltage MOSFETs Semiconductor device modeling Power system modeling Power supplies Throughput Noise reduction
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in