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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kuan-Hung Chen Shi-Chung Chang Tzi-Dor Chiueh Luh, P.B. Xing Zhao |
| Copyright Year | 2001 |
| Description | Author affiliation: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Kuan-Hung Chen) |
| Abstract | Job shop is a typical environment for manufacturing high-variety and low-volume discrete parts. Good scheduling is critical and challenging to the competitiveness of job shops. The Lagrangian relaxation neural network (LRNN) provides an approach of quantifiable quality and successful industrial applications. To further speed up scheduling for large-scale problems, in this paper, the parallelism of the LRNN approach is exploited for hardware implementation. New designs include a SIMD architecture, its associated instruction set and detailed circuits. Logic level simulation of the circuit design shows consistent schedules with those obtained by a software implementation. The hardware implementation is expected to have a one to two orders speed-up over the software one. |
| Sponsorship | IEEE Circuits & Syst. Soc |
| Starting Page | 530 |
| Ending Page | 533 |
| File Size | 462811 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780366859 |
| DOI | 10.1109/ISCAS.2001.922291 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-05-06 |
| Publisher Place | Australia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Job shop scheduling Problem-solving Hardware Lagrangian functions Neural networks Manufacturing industries Large-scale systems Computer architecture Circuits Logic design |
| Content Type | Text |
| Resource Type | Article |
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